JPS6468829A - Arithmetic unit - Google Patents

Arithmetic unit

Info

Publication number
JPS6468829A
JPS6468829A JP62226895A JP22689587A JPS6468829A JP S6468829 A JPS6468829 A JP S6468829A JP 62226895 A JP62226895 A JP 62226895A JP 22689587 A JP22689587 A JP 22689587A JP S6468829 A JPS6468829 A JP S6468829A
Authority
JP
Japan
Prior art keywords
input data
data
information
arithmetic
fields
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62226895A
Other languages
Japanese (ja)
Other versions
JP2613223B2 (en
Inventor
Masaharu Miura
Shunpei Kawasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Ltd
Priority to JP62226895A priority Critical patent/JP2613223B2/en
Priority to KR1019880011037A priority patent/KR970002391B1/en
Priority to EP19880308229 priority patent/EP0307166A3/en
Publication of JPS6468829A publication Critical patent/JPS6468829A/en
Priority to US07/513,034 priority patent/US5327543A/en
Application granted granted Critical
Publication of JP2613223B2 publication Critical patent/JP2613223B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30192—Instruction operation extension or modification according to data descriptor, e.g. dynamic data typing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Computing Systems (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To quickly operate data whose structure has first and second information fields, by providing a preserving means which preserves information in a prescribed second information field of input data as arithmetic result output data. CONSTITUTION:A tag field TFa of one input data A0-A15 is masked with logical '0' in case of OR, exclusive OR, addition, or the like and the tag field TFa of one input data A0-A15 is masked with logical '1' in case of AND, subtraction, or the like to execute the arithmetic logic operation between a pair of input data. When carry is transmitted from lower digits to upper four-bit arithmetic results D15-D12 at this time, the result of arithmetic logic operation between data fields DFa and DFb is included in arithmetic results D0-D15 and information B15-B12 in tag fields TFb of input data B0-B15 are preserved as they are. Thus, the arithmetic logic operation of data with tags is quickly executed in one step.
JP62226895A 1987-09-10 1987-09-10 Arithmetic unit Expired - Fee Related JP2613223B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP62226895A JP2613223B2 (en) 1987-09-10 1987-09-10 Arithmetic unit
KR1019880011037A KR970002391B1 (en) 1987-09-10 1988-08-30 Data processor
EP19880308229 EP0307166A3 (en) 1987-09-10 1988-09-06 Data processor
US07/513,034 US5327543A (en) 1987-09-10 1990-04-23 System for selectively masking operand portions for processing thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62226895A JP2613223B2 (en) 1987-09-10 1987-09-10 Arithmetic unit

Publications (2)

Publication Number Publication Date
JPS6468829A true JPS6468829A (en) 1989-03-14
JP2613223B2 JP2613223B2 (en) 1997-05-21

Family

ID=16852267

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62226895A Expired - Fee Related JP2613223B2 (en) 1987-09-10 1987-09-10 Arithmetic unit

Country Status (4)

Country Link
US (1) US5327543A (en)
EP (1) EP0307166A3 (en)
JP (1) JP2613223B2 (en)
KR (1) KR970002391B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5201056A (en) * 1990-05-02 1993-04-06 Motorola, Inc. RISC microprocessor architecture with multi-bit tag extended instructions for selectively attaching tag from either instruction or input data to arithmetic operation output

Families Citing this family (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03248226A (en) * 1990-02-26 1991-11-06 Nec Corp Microprocessor
JPH05324847A (en) * 1992-05-13 1993-12-10 Nec Corp Lsi for graphic drawing device
US5651121A (en) * 1992-12-18 1997-07-22 Xerox Corporation Using mask operand obtained from composite operand to perform logic operation in parallel with composite operand
DE4304198A1 (en) * 1993-02-12 1994-08-18 Itt Ind Gmbh Deutsche Method of speeding up the data processing of a signal processor
US5751614A (en) * 1994-03-08 1998-05-12 Exponential Technology, Inc. Sign-extension merge/mask, rotate/shift, and boolean operations executed in a vectored mux on an ALU
US5590352A (en) * 1994-04-26 1996-12-31 Advanced Micro Devices, Inc. Dependency checking and forwarding of variable width operands
DE69516817T2 (en) * 1994-11-14 2000-12-07 Nec Corp., Tokio/Tokyo Peripheral device for executing bit field commands
NL9401923A (en) * 1994-11-17 1996-07-01 Gti Holding Nv Method and device for processing signals in a safety system.
IL116210A0 (en) * 1994-12-02 1996-01-31 Intel Corp Microprocessor having a compare operation and a method of comparing packed data in a processor
KR100329338B1 (en) * 1994-12-02 2002-07-18 피터 엔. 데트킨 Microprocessor with packing operation of composite operands
US6643765B1 (en) * 1995-08-16 2003-11-04 Microunity Systems Engineering, Inc. Programmable processor with group floating point operations
US5826071A (en) * 1995-08-31 1998-10-20 Advanced Micro Devices, Inc. Parallel mask decoder and method for generating said mask
US6385634B1 (en) * 1995-08-31 2002-05-07 Intel Corporation Method for performing multiply-add operations on packed data
US7395298B2 (en) * 1995-08-31 2008-07-01 Intel Corporation Method and apparatus for performing multiply-add operations on packed data
JP3433588B2 (en) * 1995-10-19 2003-08-04 株式会社デンソー Mask data generation circuit and bit field operation circuit
US5815421A (en) * 1995-12-18 1998-09-29 Intel Corporation Method for transposing a two-dimensional array
US5907842A (en) * 1995-12-20 1999-05-25 Intel Corporation Method of sorting numbers to obtain maxima/minima values with ordering
US20030068623A1 (en) * 1997-06-16 2003-04-10 Genentech, Inc. Secreted and transmembrane polypeptides and nucleic acids encoding the same
US6219662B1 (en) 1997-07-10 2001-04-17 International Business Machines Corporation Supporting database indexes based on a generalized B-tree index
US6192358B1 (en) 1997-07-10 2001-02-20 Internatioanal Business Machines Corporation Multiple-stage evaluation of user-defined predicates
US6266663B1 (en) 1997-07-10 2001-07-24 International Business Machines Corporation User-defined search using index exploitation
US6278994B1 (en) 1997-07-10 2001-08-21 International Business Machines Corporation Fully integrated architecture for user-defined search
US6253196B1 (en) 1997-07-10 2001-06-26 International Business Machines Corporation Generalized model for the exploitation of database indexes
US6285996B1 (en) 1997-07-10 2001-09-04 International Business Machines Corp. Run-time support for user-defined index ranges and index filters
US6052522A (en) * 1997-10-30 2000-04-18 Infineon Technologies North America Corporation Method and apparatus for extracting data stored in concatenated registers
US6041404A (en) * 1998-03-31 2000-03-21 Intel Corporation Dual function system and method for shuffling packed data elements
US6125406A (en) * 1998-05-15 2000-09-26 Xerox Corporation Bi-directional packing data device enabling forward/reverse bit sequences with two output latches
US6065066A (en) * 1998-06-02 2000-05-16 Adaptec, Inc. System for data stream packer and unpacker integrated circuit which align data stored in a two level latch
US6389425B1 (en) 1998-07-09 2002-05-14 International Business Machines Corporation Embedded storage mechanism for structured data types
US6209012B1 (en) * 1998-09-02 2001-03-27 Lucent Technologies Inc. System and method using mode bits to support multiple coding standards
JP3744285B2 (en) * 1999-10-29 2006-02-08 日本電気株式会社 Shift register and control method thereof
GB0024312D0 (en) 2000-10-04 2000-11-15 Advanced Risc Mach Ltd Single instruction multiple data processing
US6542963B2 (en) * 2001-01-10 2003-04-01 Samsung Electronics Co., Ltd. Partial match partial output cache for computer arithmetic operations
US6738792B1 (en) 2001-03-09 2004-05-18 Advanced Micro Devices, Inc. Parallel mask generator
US6937084B2 (en) 2001-06-01 2005-08-30 Microchip Technology Incorporated Processor with dual-deadtime pulse width modulation generator
US6552625B2 (en) 2001-06-01 2003-04-22 Microchip Technology Inc. Processor with pulse width modulation generator with fault input prioritization
US6976158B2 (en) 2001-06-01 2005-12-13 Microchip Technology Incorporated Repeat instruction with interrupt
US6601160B2 (en) 2001-06-01 2003-07-29 Microchip Technology Incorporated Dynamically reconfigurable data space
US7003543B2 (en) * 2001-06-01 2006-02-21 Microchip Technology Incorporated Sticky z bit
US6985986B2 (en) * 2001-06-01 2006-01-10 Microchip Technology Incorporated Variable cycle interrupt disabling
US6728856B2 (en) 2001-06-01 2004-04-27 Microchip Technology Incorporated Modified Harvard architecture processor having program memory space mapped to data memory space
US7020788B2 (en) 2001-06-01 2006-03-28 Microchip Technology Incorporated Reduced power option
US6604169B2 (en) 2001-06-01 2003-08-05 Microchip Technology Incorporated Modulo addressing based on absolute offset
US6975679B2 (en) 2001-06-01 2005-12-13 Microchip Technology Incorporated Configuration fuses for setting PWM options
US6952711B2 (en) 2001-06-01 2005-10-04 Microchip Technology Incorporated Maximally negative signed fractional number multiplication
US6934728B2 (en) 2001-06-01 2005-08-23 Microchip Technology Incorporated Euclidean distance instructions
US7007172B2 (en) 2001-06-01 2006-02-28 Microchip Technology Incorporated Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection
US20020184566A1 (en) 2001-06-01 2002-12-05 Michael Catherwood Register pointer trap
US7467178B2 (en) 2001-06-01 2008-12-16 Microchip Technology Incorporated Dual mode arithmetic saturation processing
US20040021483A1 (en) * 2001-09-28 2004-02-05 Brian Boles Functional pathway configuration at a system/IC interface
US6552567B1 (en) 2001-09-28 2003-04-22 Microchip Technology Incorporated Functional pathway configuration at a system/IC interface
US7430578B2 (en) * 2001-10-29 2008-09-30 Intel Corporation Method and apparatus for performing multiply-add operations on packed byte data

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62154023A (en) * 1985-12-26 1987-07-09 Panafacom Ltd Mask read control system for operand data

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4139899A (en) * 1976-10-18 1979-02-13 Burroughs Corporation Shift network having a mask generator and a rotator
US4241396A (en) * 1978-10-23 1980-12-23 International Business Machines Corporation Tagged pointer handling apparatus
FR2455315B1 (en) * 1979-04-23 1986-10-24 Anvar METHOD FOR PROVIDING A NUMERICAL CALCULATION RESULT WITH THE NUMBER OF SIGNIFICANT ACCURATE NUMBERS IN THIS RESULT AND NUMERICAL CALCULATION DEVICE IMPLEMENTING THIS METHOD
FR2550362A1 (en) * 1983-08-05 1985-02-08 Cazor Denis Automatic unit for processing uncertainties in digital arithmetic processors.
JPS6123998A (en) * 1984-07-13 1986-02-01 株式会社日立製作所 Method of regenerating spent sodium fluoride adsorbent
US4896258A (en) * 1985-07-04 1990-01-23 Hitachi, Ltd. Data processor provided with instructions which refer to both tagged and tagless data
US4847802A (en) * 1986-06-12 1989-07-11 Advanced Micro Devices, Inc. Method and apparatus for identifying the precision of an operand in a multiprecision floating-point processor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62154023A (en) * 1985-12-26 1987-07-09 Panafacom Ltd Mask read control system for operand data

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5201056A (en) * 1990-05-02 1993-04-06 Motorola, Inc. RISC microprocessor architecture with multi-bit tag extended instructions for selectively attaching tag from either instruction or input data to arithmetic operation output

Also Published As

Publication number Publication date
EP0307166A2 (en) 1989-03-15
US5327543A (en) 1994-07-05
EP0307166A3 (en) 1991-03-27
JP2613223B2 (en) 1997-05-21
KR970002391B1 (en) 1997-03-05
KR890005608A (en) 1989-05-16

Similar Documents

Publication Publication Date Title
JPS6468829A (en) Arithmetic unit
ES311414A1 (en) Data processing system
DE68926557D1 (en) Fuzzy computer system
Kondo Knots of unknotting number 1 and their Alexander polynomials
Kronk et al. A 4-color theorem for toroidal graphs
JPS57155675A (en) Input system of symbol command
JPS6426236A (en) Data driving type computer
GB969572A (en) An arithmetic unit for a digital computer
Hille Binary trees and permutations.
SU693371A1 (en) Series-action arithmetic device
JPS56105505A (en) High-speed sequence control device with numerical operation function
SU1444760A1 (en) Device for squaring a sequential series of numbers
JPS6441026A (en) Integrated circuit
JPS57164334A (en) Operating device
JPS6435630A (en) Information processor
JPS6441970A (en) Vector arithmetic unit
JPS54159822A (en) Character processing system
GB1010334A (en) Tunnel diode logic circuits
Narendran Complexity of E-Unification Problems
Bonet et al. A split control store VLSI for 32 kbps ADPCM transcoding
JPS6419468A (en) Arithmetic logic circuit
JPS6476126A (en) Data processor
GB1501226A (en) Arithmetic units
JPS56164440A (en) Data train processing device
JPS6438863A (en) Document processor

Legal Events

Date Code Title Description
S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313117

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees