DE2251876B2 - ELECTRONIC DATA PROCESSING SYSTEM - Google Patents

Description

The invention relates to an electronic data processing system with externally connected data sources according to the preamble of claim 1.

Digital computing technology has evolved to be relatively economical and fast data processing steps can be carried out with a high degree of flexibility. Most data processing systems can use the input / output devices associated with the processor are used for data exchange involving buffering, queuing and allows other techniques, since such devices generally do not require rapid reactions will. However, data acquisition and process control typically require very fast Responses and the assumption of control functions of the central processing unit, so that such tasks can be taken into account in certain applications. For example, concerns the computer-controlled process control in general the acquisition of analog and digital Data from an industrial or similar process, the calculation of the tax corrections to the ensure proper functioning of the process and the application of suitable control signals on the controls of the process on a

ίο quick and timely manner. To do this effectively to be, the acquisition, the calculation and the generation of control functions must be stirred in real-time operation will. That is, the delay between data acquisition from a variety of sources and controlling the functions or processes that are involved must be such that the effectiveness of the control is not lost. For many uses this means that the delay may only be a fraction of a second, although others Applications that can be handled by the same system have delays of hours allow. The time between a “stimulus”, for example from analog or digital sources and the response or response of the system, is often referred to as the interrupt response time, and it is the most important variable in real-time computer systems. Experience has shown that such Stimuli that require the shortest interrupt response times in a system, often by a short simple coding are characterized by a use of conventional input / output auxiliary sources (Resources) do not require and often do not allow.

The known systems for data acquisition and process control always have between the response time differentiated, which is required by a complex of input / output devices, by setting interrupt priority levels for these devices. Therefore, an interruption from an input / output device of low priority may occur is processed by a controlling processor, but this processing can itself again interrupted by an interruption resulting from a higher priority rank, the later occurs for another input / output device. For this purpose, the known data processing systems use fixed priority level arrangements for each Input / output device, so that it always fought for the attention of the processor at this stage, which resulted in the need to rewire the device to change its priority level became. Even if an interruption occurred with a higher level priority, the known processors required a sequence of special condition routines for the purpose To input data corresponding to the status of the interrupted process into memory so that these could be visited again later and loaded into the control circuits of the processor, after the interruption has been satisfied with the higher priority level. Such a procedure made it necessary to accept the delay times caused by this storage procedure were added, with additional delays resulting from the stored Data had to be looked up again at a later time. Additional delays are also used by the known systems

required to identify the source of the interruption and to gain status identifying signals before servicing the request is continued. In addition, the interrupted program was also resumed often disturbed by program errors. The processor also required facilities for the determination the appropriate service subroutine before the interrupt could be handled.

Many requirements for data acquisition and / or process control deal with the Data exchange and with control functions that meet their requirements in terms of timeliness the system response will vary from time to time. For example, some applications can be relatively slow responses for a specific data exchange or a specific control function allow relatively long time periods, but for other time increments they require essentially instantaneous ones Answers and controls. ao

The problem of choosing a program designed with the highest urgency is the other Allowing programs or parts of programs to be interrupted in their favor is also known per se and is described in DT-AS »5 14 99 200, for example. The solution suggested here makes use of program control words, which are available programs or subroutines and also describe programs or subroutines that have already been interrupted. To control the Priority-controlled program interruption, a control circuit is provided which is known per se Initiation of a subroutine of different priority each energizes control devices that are in are each assigned to a subroutine in a known manner. They also complement the active when aroused Program status word and store it in the inactive assigned to the relevant sub-program Program status word register and also transmit the program status word assigned to this subroutine into the active program status word register.

However, the above-mentioned methods and arrangements are for real-time processing in the Data acquisition and process control too slow.

It is therefore the object of the invention to provide an electronic data processing system that is also extends to the data processing in real-time operation, specify in which the real-time responses can be generated much faster. In addition, the processors, input / output devices and / or the interface operation between these named units for data acquisition and process control take into account the system's relatively quick reactions with regard to their selected configuration can take. Therefore, a virtual processor organization should be specified, which in particular is particularly suitable for the named tasks of data acquisition and process control. In this The task also includes the subtask of providing options that enable flexible priority allocation.

These tasks are achieved by those specified in the characterizing part of claim 1 Characteristics.

The subclaims relate to advantageous configurations and developments of the subject matter the invention.

The advantages of the invention are that the data processing system has the following, particularly favorable for the implementation of data acquisition and process tasks Properties were given. These properties and thus the advantages of the invention result from the fact that the processor has several control components which are organized so that different Tasks based on priority interruption levels with a minimum of wasted time by the Switching between these stages can be carried out.

The advantages also include the fact that input / output modules are provided that are dynamic have assignable interrupt priority levels. You are also able to get address information dynamically store associated with the service subroutines stored in a control processor are. Furthermore, the input / output modules can be masked individually by the main processing system will.

In addition, the input / output modules can monitor their own status and send a signal to a Control processor transmitted, which indicates whether a change in the state is required or not.

Another advantage of the invention is that real-time responses of the system to dynamic externally changeable requirements can be set while substantial additional program processing is carried out is carried out in the control processor.

Finally, with the help of the invention, a polymorphic Data processing system that is able to respond to varying inputs / Adjust output requirements on a dynamic basis.

Embodiments of the invention are shown in the drawings and will be described below described in more detail. It shows

F i g. 1 is a system block diagram showing the general Environment of various system components and other processors to which the present Invention is related,

Figure 2 shows the relationship of some features of the present Invention particularly for the assignment, handling and unit masking of interrupt service requests using priority assignments,

Fig. 3 some of those related to the priority level Multiprocessor control components that allow a processor according to the inventive concept, as virtual machine to work,

F i g. 4 the general format of some instructions.

F i g. Fig. 5 shows a typical arrangement of a portion of the processor memory used for the recovery of Subroutines can be addressed to operator calls on different ones, from an interrupt to deliver originating control signals.

6 shows some important components for the interface circuits between a processor, a direct channel control and some Ε / Λ devices connected to the channel,

F i g. 7 shows some of the components in a typical I / O device and how they relate to that of FIG. 6 interface multiplexing circuit and

F i g. 8 an arrangement of a further, in

_bM "" _em U of the use of the invention

Instruction.

Detailed description of the exemplary embodiments

I - Introduction _The in the ^ leadership ^^ even.

Devices and the ^Pr ° ^ V ^process "Ed teuerunß applications Datenerf" J ⁿ f ^ "f

provided «» ^d ™. ^ * ^ ™ "" Αβΐηα realizes numerous ^ ™ u ^ me «m but also in a system that requires real-time processing

running routines and using
the triggering VorßW * ™
between one out of loosely
on expected answer wid often
Answer interrup _u chun | ze _lt

Sat

dar- _or

x ₅

. _ao

of interruption pnonta
as requested by the program ^^ or dynamically new ^^^ usgerS and processor is with register «^ level _so sees conditions ^ r every interruption

before that the concept ^ "^" ^^ J with machine equipment ν rw ™ ^w ^ ™ interruption a very ^sc ^. ⁿ ^ S _n , as

enables. The ^Umscha S | _n X _n ^ mS the emergency part of the interruption ^ handtang umgd> t_ * e ^ _ agility of Pf ?grammrettimgs rungsoperattonen. The ^{process was aroused}

Invention can be either as a remote emes ^ anaDn g

g »£ ^d Ä

Acquisition and control ™ 8 "^ 'J ^r ^ Sistungsvariablen Area of the entire system

requirements important. F / ^ l devices by

The processor has entered a different channel from its I / O. Elements of the channel functions which are described as an interrupt controller. The Kanri ^ " _{modules can be connected to the} ^built-in sTdttstelle. Jed"? EM module should continue to include 64 devices ^{in d} "^^ ^; _u ^{K a} _{n stage interrupt processing} , which was previously _{only possible through} programming,

2. the extremely short status changeover time due to the aut -n ^ -fc-JB ^ «

information (with status) of the source of the interruption,

₃ . _{d · Choosing} a set of instructions that is optimized for fast, simple, interrupt-induced subroutines

^^ summary quick, open ended

. Treatment possibility, ⁵ connection possibility to another pro ^ _influencing priority sub-

breaks and class breaks and _{? the} provision of extremely descriptive, unambiguous status designations that allow easy program repetition for machine and program

^ _{LU and contains an instruction address.} The operation register (OP) is also 16 bits in size, but is loaded from memory and _contains | _the first word of all instructions. The memory data register (SDR) can hold 16 bits and one pantätsbyte. It is loaded from the memory, the data bus or from data switches. It optionally drives the direct control channel <o DCC, the memory or the Y-collecting line. The ' _heradre ' _{register {SAR) is 16} bits in size if the ^ ^ _{γ data bus} or the IAR loaded _the ^^ _memory address. ^ ^ _{γ y} . _{Collective lines for} operands

^ Lt / is a 16-bit parallel combination _{circuit for} two operands. One operand is delivered through the / ILU collective line, the other through the yth register and / or the forced line. g _{can add j} and subtract the

Operations AND, OR and XOR _{Sj are also used to} calculate the address

used.

Memory group

_{In order to enable} fast status switching ^ _n ^ ^ _per and from condi-

rrrtem

Device This includes the
cation control adapter / ICC / I,

adapter and two interval timers. _

Sge new aspects of the explained datemerar l are

rX ^^ P ^ u ^ st ^ _D Te switching between register _{banks to, ^ the cntsprcche} nden stage, st an auto-

i _tihc machine part function. The registers belonging to one of _{these are only used} .

609 512/25;

9 * 10

is used when the processor is working at this stage. Overflow indicator
This multi-level redundant register configuration

is in Fig. 3 shown. As soon as the result of an addition or sub-hierarchy from the capacity of the system for the interrupt handling operation, the levels are a priority. In this example 5 steps are taken, ie a result is generated which is either level 0 as the highest level and level 3 as greater than 2 ¹⁵ -1 or less than - 2 ¹⁵ , a lowest occurs. Overflow condition on. The processor recognizes that the four accumulators ACCO to ACC3 overflow condition by observing the overflow (Fig. 3) are each provided for one level and sluggish into and out of the high-value bit position (project 16 bits each. In addition, four // 1Ä -Back- io character position). If the transfers are not intended for overlapping registers IARBO to IARB 4 (1 per vote, there is an overflow condition, sonsl level). Each has 16 bits. Their function is not. There are four options:
the support of the IAR in a stage-to-stage, _{Kejn über hindn and kdn über} transition and this eliminates the need to save the IAR through programming. » _{5 2} carry in and carry out. (over-each of the index registers (XRl bs * i? 7) w, rd four- _{trg st} ^ _{men überjn} _ _no 5 _overflow)

Tr i? RT HP ti hl ^{reP m} " ³ · ^{Carry in} ' ^{but no} carry out.

contains 16 bits and a pantat byte (transfers do not match - overflow.)

As can be seen in Fig. 3, the working _{4 is carried} out, but no carry is on. (Over storage group (index register) of the data collection 1- * o _{agree not over} _ _overflow ⁸ _uf .)
line loaded and its contents in the Y-collective- '
headed. Parity check is in the group. The overflow indicator is only reset if provided. he either checked by the conditional jump or the conditional branch instruction and that

35 overflow escape character (bit 8) is zero and

The memory used is preferably a bit 15 in the condition mask is equal to one,

monolithic memory and in steps of carry and overflow contain the condition

2 K words by 18 bits with parity byte up to code that follows a P / O instruction. Carry over "is

organized a maximum of 16K words. Bit 0 of the condition code and overflow

monolithic memory matches magnetic memory 30 bit 1. With the transfer, the summary also becomes

and is volatile. The bipolar monolithic status bit (S-bit) is held in the event of interruptions.

Memory unit also matches the logical signals. There are also zero, equal, plus and

of the processor. The group modules and support minus indicators are available. These scoreboards will be

modules are located on the memory card, also as ^ the result of a logical or arithmetic

which contains 2048 words by 2 bits. Access and operation set.
Cycle time, measured on the memory card

125 nanoseconds or 400 nanoseconds. The IV — number representation
The memory module comprises 4 chips or 512 bits and is All operands are preceded by integers. A stacked module with two substrates that each handle characters, with the sign bit as the two chips. 40 leftmost bit is considered. Positive numbers ΙΠ - arithmetic indicators are shown in real binary notation, with ^the y ° ™ ichenbit being set to 0 for the carry indicator. Negative numbers

are shown in their two's complement, and

The carry indicator is set when the sign bit is set to 1. The two-way operation has produced a result which is the complement of 45 of a number is obtained by reversing it physical capacity of the accumulator over each bit of the number and adding a 1 in dei increases. The carry-over indicator has the following lowest-value bit position.

Three conditions are set: This type of number representation can be used as the lower-value part of an unlimited length of representation

1. For a non-circular left shift operation, 50 number should be considered. When the number is positive if the last of the sign position is 0, all bits to the left of the highest bit are representative excavated bit was a one bit; Bit of the number including the sign bit zero

2. In the case of an arithmetic instruction, if a carry If an operand is therefore made with high-value bits from bit 0 (sign bit). This can be done if this extension is obtained regardless of the polarity of the operand concerned. If a large negative number is added, as the significant bit of the operand stands for a smaller positive number or the like added. The highest positive number is subtracted from the number, and the carry indicator divides the polarity of the result 60 _with a sign bit 0, while the largest is negative, is available to the program from an integer field made up of all ones. As soon as no carry takes place, the tive number from an integer field with loud) result is negative and should be positioned again with complementary zeros with a one bit in the sign bit; tion exists.

3. in a subtraction operation when a boron., _T

gen occurs beyond BitO. Before each Addi- 65 V instruction class

tion, subtraction and non-circular links- der in a processor after execution

Shift operation, the instruction set used for transmission display provides at minima

ger automatically reset. len costs sufficient skills to exportunj

simple arithmetic and logic functions and for controlling the units and their interfaces with another processor system. The instruction salt is divided into classes. Generally give the classes the type of operation to be performed.

Load and Save - These instructions transfer operands between main memory and the processor. They are: Load and Zero, Load Accumulator, Save Accumulator, Direct Load, Save index and load long index.

Arithmetic - These instructions perform arithmetic Operations between operand main memory and / or in the processor. They are: addition, Complement registers, addition registers and subtraction registers.

Logical - These instructions perform logical operations between operands in main memory and / or in the processor. They are: logical AND, logical complementary, logical OR, AND register, Antivalent register and OR register.

Shift — These instructions shift an index register or the accumulator left or right. Sie s ^: nd: Left shift Logical, Right shift Logical, Right shift Arithmetic and Left shift Circulation.

Branch - This includes addition to memory and jump, conditional jump, branch and link, conditional branch, branch around 'branch and long link.

Input / Output - The instruction controls the setting of interrupts and communication with I / O units. It reads: Execute input / output.

Register-to-Register - These instructions move data between the control registers, index registers, IAR and accumulator. They are: loading from register, saving in register, query level and mask, inspection IAR access register, loading processor status, exchange register, AND according to mask and OR according to mask.
State Control - These instructions change the state of the processor. They are: Exit and Stop stage.

VI - instruction format

Two instruction formats are provided. The short instruction format is 16 bits long as shown in Fig. 4A and the long instruction format is 32 bits long as shown in Fig. 4B. Each of the two formats is divided into different fields that indicate the operation and how it is performed. Although most fields have the same meaning from one instruction to the next, some of them also have special instruction-dependent meanings. The OP code field is 5 bits long and indicates the instruction operation to be carried out. The field is 3 bits long and controls the use of the index, accumulator and instruction address register. The displacement field DISP is S bits long and controls the execution of instructions and / or generation of the effective address, depending on the information in the OP code and in the field. The address field is 16 bits long. In the long instruction format it is used for effective address generation, with the exception of the ΡΙΟ instruction, where it is used as part of the I / O command. Most instructions refer to a location in main memory that contains the instruction operand. The address of this point is called the effective address (EA) . There are two methods of generating the effective address: one for the short instruction format and one for the long instruction format.

In the brief instruction format shown in FIG. 4A, the λ field and the displacement field DISP are used together to generate the effective address. The i? Field indicates the instruction address register (IAR), the accumulator (A) or an index register (XR) . However, the accumulator is not used for one of the operands for effective address generation.

R = 000 instruction address register or accumulator

R = 001 index register 1
R = 010 index register 2
R = 011 index register

R = 100 index register 4
R = 101 index register 5
R = 110 index register 6
R = 11 i index register 7

The displacement (DISP) is an 8-bit number, the high-order bit of which is the sign bit. Negative shifts are in two's complement form. If they are used to generate an effective address, the sign bit is updated through the high-value positions. The effective address is generated as follows:

EA = [IAR] + DISP for R = 000
EA = [XR] + DISP for R = 000

(Except short conditional branch, where the effective address is the contents of the /? Register is).

In the long format, the shift of bits 8-15 is the direct field. An exception to this for all long instructors is Load Index Long (PLXL), EA = address field.

VII - instruction description

Load accumulator - PL: The content of the main memory parts specified by the effective address replaces the content of the accumulator. The content of the main memory remains unchanged. Overflow and overflow indicators remain unchanged. Depending on the operands stored in the accumulator, the other indicators are changed with this instruction. The new value is retained and can be checked until another instruction changes the display. If the Λ field is 0, the effective address is relative to IAR.

Load and zero - zip code: This instruction has the same effect as load accumulator short, but has the additional function that the main memory location specified by the effective address is set to zero. This instruction changes the other indicators depending on the operand stored in the accumulator. The new who remains and can be checked until another instruction changes the display. Carry over and overflow indicators remain unchanged.

Load direct - PLI: The accumulator or an index register are loaded with the specified operan

the loaded. The register to be loaded is indicated by the i? -Feid of the instruction: A field of 0 denotes the accumulator. The shift field of the instruction forms the operand to be loaded directly. The 8-bit operand is expanded to a 16-bit operand by updating of the sign bit value through the high-value bit positions. Carry over and overflow indicators remain unchanged. With this instruction the other indicators become dependent on the one in the R register loaded operands changed. The new value remains and can be checked until a another instruction changes the display.

Load Index Long - PLXL: This instruction essentially follows the format shown in Figure 4B, with the exception of bits 5 to 7 which form the R 1 field, while bits 8 to 10 form the R 2 field. Bits 11 to 15 must be zero. The effective address is:

EA = content (R 2) + address R 2 φ 000 ^ao EA = address R2 = 000

The content of the effective address forms the 16-bit operand that is loaded into the register specified by the R 1 field. as

Al = 000 -ACC

Rl = 000 - no indexing

ÄlorK2 = 001 -XRl

RIoAnRl = QlQ-XRl

KloderK2 = 011 - XR3

RloderRl = 100-ÄTÄ4

Al or Rl = 101 -XRS

Rlodcr Rl = UO-XR6 RloderRl = 111 - XRl

The carry-over and overflow indicators remain unchanged. With this instruction the other indicators are changed depending on the operand loaded in the R 1 register. The new value is retained and can be checked until another instruction changes the display.

Store Accumulator - PST: The short format in Figure 4A is followed as with most of the instructions described herein unless otherwise noted. The content of the accumulator replaces the content of the main memory location specified by the effective address. A field with the value 0 denotes the IAR: a field other than zero denotes an index register. The contents of the accumulator as well as the carry and overflow indicators remain unchanged. With this instruction the other indicators are changed depending on the operand stored at the effective address. The new value is retained and can be checked until another instruction changes the display.

Store index - PSTX: The effective address is formed by the sum of the contents of the IAR and the shift. The content of an index register or zero replace the content of the main memory location specified by the effective address. The register to be stored is indicated by the R field, in which a 3-bit binary number denotes the register (e.g. R = 001 denotes the register XR1, while R = 111 denotes the register XR 7). When R - 000, a zero is stored in the effective address.

The content of the specified register as well as the carry and overflow indicators remain unchanged. With this instruction the other indicators become dependent on the one at the effective address stored operands changed. The new wen remains and can be checked until a another instruction changes the display

Addition - PA: The content of the main memory location specified by the effective address is added to the content of the accumulator. The result replaces the content of the accumulator. The content de; Main memory remains unchanged With this instruction, the indicators are changed depending on the result loaded into the accumulator. The new value is retained and can be checked until another instruction changes the display. A zero field denotes the IAR.

Subtract - PS: The content of the main memory location specified by the effective address is subtracted from the content of the accumulator, and the difference replaces the content of the accumulator.The content of the main memory remains unchanged.This instruction changes the indicators depending on the result loaded into the accumulator . The new value is retained and can be checked until another instruction changes the display. A K field of zero denotes da; IAR.

Logical AND - PN: The content of the main memory location specified by the effective address is AND-linked bit by bit with the content of the accumulator. The result replaces the content de; Accumulator. The content of the main memory as well as the carryover and overflow indicators remain unchanged. With this instruction, the other indicators are changed depending on the result loaded into the accumulator. The new value is retained and can be checked until another instruction changes the display. A field of NuI denotes the IAR.

Logical OR - PO: The content of the main memory location specified by di <effective address is bit-by-bit with the content of the accumulator; OR linked. The result replaces the content of the accumulator. The content of the main memory ;: as well as the carryover and overflow indicators remain unchanged. This instruction changes the other indicators depending on the result loaded into the accumulator. The new value persists and can be checked until a change instruction changes the display. An A field of NuI denotes the IA R.

Logically complementary - PX: The content of the main memory location specified by the effective address is linked bit-by-bit complementarily with the content of the accumulator. The result replaces the contents of the accumulator. The content of the main memory as well as the carry and overflow display remain unchanged. With this instruction the other indicators are changed depending on the result loaded in the dci accumulator. The new value remains and can be checked until another instruction changes the display. Eil R field of zero denotes the IAR.

Register - Accumulator Instructions: PAR, PSR PNR, POR, PXR, PSTR, PLR, PCR, PSLM, PIR PIPS, PUB.

An arithmetic or logical operation, i

Prescribed by the M field bits 12 to 15 in Fig. 4A) wild, is executed between the contents of a register and the contents of the accumulator. These operations are:

M = I addition [PAR)

M = I subtraction (PSR)

M = 3 AND link (PNR)

M = 4 OR link (POR) and

M = 5 complementary link (PXR)

The result is placed in the accumulator. The subtraction operation (PSR) subtracts the index register from the accumulator. Indicators are affected as for the corresponding store accumulator instructions (PA, PS, PN, PO, PX). An R field of zero denotes the accumulator, an R field other than zero denotes an index register.

Also means

M == 6 memory to register (PSTR), while M = ■ = 7 indicates loading from register (PLR).

The accumulator content is stored in a register indicated by the R field (PSTR) or the content of the register indicated by the K field, or the content of the register indicated by the R field is loaded into the accumulator (PLR). Carry over and overflow indicators are not changed. With. These instructions change other indicators depending on the operand involved. The new value remains and can be checked until other instructions change the indicators. The source register is not changed in PLR. An R field of zero denotes the IAR, a field other than zero denotes an index register.

M = 8 selects the complement register (PCR). The register indicated by the R field is complemented in two ways. The result is placed in the Λ register. An R field of zero denotes the. Accumulator, a non-zero R field, an index register. The transfer indicator is not changed: If the number to be complemented is the highest negative number that can be displayed in the accumulator, the overflow indicator is set. With this instruction the other indicators are changed depending on the result in the R register. The new value remains and can be checked until another instruction changes the indicators.

M = 9 corresponds to the instruction level and mask sensing (PSLM). The currently active level is set in binary coded format in bit positions 14 and 15 of the register indicated by the R field. The content of the mask register is set in bit positions 0 to 3. The bit positions ui 4 to 13 are set to zero and the mask is not changed. The carry-over and overflow indicators are not affected. This instruction changes the other indicators depending on the operand loaded into the R register. The new value remains and can be checked until another instruction changes the indicators. An R field of zero denotes the accumulator, an R field other than zero denotes an index register. If bit 11 in the instruction is set to 1, the mask is diverted but not changed. No interruption can occur. This state continues until a PNM or PO Vf instruction is executed. This provides a summary mask function.

M = A selects an exchange register (PIR). The accumulator content is stored in the register indicated by the R field and the content of the register indicated by the R field is loaded into the accumulator. If the R field is equal to zero, no operation takes place on the basis of this instruction. Carry over and overflow indicators are not changed. With this instruction, the other indicators are changed depending on the operand set in the accumulator from the R register. The new value remains and can be checked until another instruction changes the indicators.

M = B corresponds to the instruction Load Processor Status (PLPS). The processor status is loaded into bit positions 0 to 9 of the R register. R = 000 denotes the accumulator. Carryover and overflow indicators are not affected. With this instruction the other indicators become dependent

»Ο from the operand loaded into the R register changes. The new value is retained and can be checked until another instruction clears the indicator changes.

M = C denotes the instruction /.4Rß-Rß-RegisterCheck (PUB). The content of the // IRß register for the selected level replaces the content of the register specified by the R field. R = OGO denotes the accumulator. If the indicated level is zero, the execution of this instruction results in the loading of zeros into the register indicated by the R field. The // IRß register remains unchanged. The level is selected by the binary coded value in bit positions 10 and 11 of this instruction. If the selected level is active or in processing and is currently running due to a request from a higher level, the carry indicator is turned on and the level is reset. If the selected level is not active or is currently running, the carry-over indicator is switched off. Therefore, if the selected level is currently running, it will be canceled, ie it will not automatically become the current level when all higher levels are energized. Even if the current level is selected, it will be energized. The overflow indicator is not affected.

With this instruction the other indicators are loaded depending on the one loaded into the R register Operands changed. The new value is retained and can be checked until other instructions are given change the indicator.

The values D to F in the M field are invalid and lead to an interruption of the program test.

Conditional jump - PSKC: The R field must be zero. Bit 8 is the overflow rescue indicator, and bits 9 to 15 become the condition field in which:

Bit 9 - condition code zero (i.e. carry

and overflow switched off)
Bit 10 = result zero

Bit 11 = result negative (high-value bit = 1) Bit 12 = result positive and not zero
Bit 13 = result equal (lower value bit = 0) Bit 14 = carry-over indicator off
Bit 15 = overflow indicator off

6o

The field comprising the seven bits 9 to 15 is used as a condition mask. The Bc-

609 512/257

19th

¹⁷ _The field comprising 7 bits 9 to 15 is called

conditions are used by a bit in the mask on _{condition sma} ske. The conditions to be checked

nvnphpn Wr> nn pinp Her specified conditions ,,,,,, ^ _n Hnrch the bits in the mask anos.

applies, the instruction address register is increased by tins & ^ ^^ _no specified conditions before the next instruction S ^eholt .. ^w '^ _{e 5} applies or no conditions are specified, the program then jumps to the _{next instruction address} register the content of the word in the normal program sequence. If no _{address field} (# = 000) or the content of an index condition are specified or the cores of the attached. ^ (R φ QOO) are loaded. If one of the specified conditions applies, there is no jump. ? applies _enes conditions, no Vemvei-When the overflow is set indicator (bit 15 in aer g ^ ^ _{next follow} d _e instruction is stipulation must be set to 1), it is ausgescuaiiei, e ^ _{If the} overflow indicator is checked overflow rescue indicator (bit 8) if s ^ ^ the _{condition must be} equal to 1), he will not be affected by any other indicator. ^ holds if the overflow rescue mark

if that

Rescue mark the overflow does not Auswar | ö ^ ^ _{is AJ] e other} indicators are

has, if the condition code 0 (Bit9) geprui ν _betfoflen rescue mark fluctuations _The overflow (ie carry and overflow mark's advertising ^ effect if the condition code 0

the unchanged by this test ;, as _{I NuJI jst The} überlaufreitungskenn-

other indicators are by this instruction _zdche ^ _can be checked (ie, transfer and

not affected. Overflow are not affected by this check.

Branching and linking - PBAL: ve _D _ _{e In;} . _{truktion nat has} no effect on the

_{Contents of the instruction address register} (the position of the '^ indicators.

The next instruction) is _{stored in the register specified by the * Shift} _ _P SLL, PSRA, PSRL, "SLC: Es R-Field. The in ^. ^ ^ _{format of the} ρi g. 4 A used with the exception of the instruction address register is then on the durcn aie ^ M.odiäiierfeld bits forming ^ _{shift number} representing bits to iS. the tive address set 8 to 10 and the sum of IAR plus shift etteK- formed 11, which _is the position of the next Removing _{R ister R d to} j number _e A jR field is shifted from zero oe ^ specified bit positions. This records the accumulator, a zero shift _number can hold any value in the range from U to 16 and the field is an index register. una _nchmen shift digit numbers with a higher value overflow indicator and other indicators ^ ^ ^ are invalid and lead to program this instruction does not affect.. .. _pr üfunterbrechung in the processor. a Ä Feid of

Branching and Long \ 'erknüpfung - ^Ρ υΑί -': - length _"beze i _c HNET the accumulator comparable from zero

The format of FIG. 4B is used, the bits »ms _here ^ .peid an index register. The bus 8 bis

But 15 must be zero. The content of the Instruk- ^^ modifier for the sliding instruc-

tion address register is stored in the "m

specified register. An R-FM of 35 · _ _Link Circular Shift (PSLC). The Regi-

NuIl denotes the accumulator, one of Nu ¹¹ J "" _{R is logical} to the left by the number of

separate R field an index register. The address field s _{t itioncn} rotated, which is in the sliding / ahl ani> c-

is loaded into the Instruktionsadreßregister and F _übert ra _g s and Überlaufanzeiccr be

will give the address of the next to be executed si _ b ^^ _lnslTukUQn ; _{earth the}

40 mem ν

will give the address of the next to be executed si _ b ^^

Instruction. Carry over and overflow indicators as well as 40 mem ν ^ _{d £ m E}

the other indicators are changed by this instruction on ^^ _Γ3ΐ > _η

g ^^ _Γ3ΐη changed The new value remains

unaffected. ..., hold and can be tested until another

Branch - PB: Replace the effective address Ja ten ^ P ^

the content of the Instruktionsadreßreg.ster and forms Instrukto _L t " _k sschicbung (PSLL). The Re-

the address of the next instruction to be executed 45 UUl g ^ ^ _ß . _after

tion. Em R field of zero denotes the MA ₁ en, g ^er ; _{overtook the number given in the} slide

Non-zero R field an index register. emptied of lower value positions

All indicators remain unchanged ■ ^ _The running indicator remains unchanged

Conditional Branch - PBC: The format of the , bit position zero of the / ^ register

Fig. 4B is used with the exception of bit 8 50 other u ^ ρ ^ _over ^

which the overflow direction identifier .s and de gsges carry indicator, a zero

Bus 9 to 15, which represent the conditions, m tine ^ ^^ _m ^ ^^ _{instruction will be} ^

which mean: _{other scoreboards} depending on the result of the

Bit 9 = condition code zero (ie overflow ₅₅ shift operation changed. The new value remains

and transfer both of) .'alten and can be eprüft _ö until another

Bit 10 - Result zero instruction changes the indicator

Bit 11 - Result negative (high value Bi. - 1) 010 - Logical right of right ^ h.eh.np (/'.SR/. Has

SS: 3SS K = ,. ₀ >. S = JSSS ¹ SSS

Bit 14 = carry-over _{indicator from M} £ of _{this instruction w} ^ _r dcn the other indicators Bit 15 - = overflow indicator off depending on the result of the shift. Mcration verIf the Λ-field is equal to zero, the instruc- changes: The new value remains and can getion long and the branch address the contents of 65 are checked until another Instrukt.on the display address field If the R-field of Changes zero differently. The cleared high bit positions are, the instruction is short and the branch registers R are set to zero
address the contents of the index register R. 011 - Arithmetic right shift (PSRA).

Register R is shifted to the right by the number of bit positions indicated by the shift number. The value of the sign (the significant bit) is entered into the cleared valued bit positions of the R register. Carry over and overflow indicators remain unchanged. This instruction changes the other indicators depending on the result of the shift operation. The new value remains and can be checked until another instruction changes the indicators.

Add Directly - (PAI): It will be shown in Fig. 4 A is used, but the operand field is expanded to 16 bits by updating the sign to the eight high-value bits 8 to 15. Then it is added to the contents of the register indicated by the field. The result is placed in the Ä register. An R field of zero denotes the accumulator, an R field other than zero denotes an index register. Carry over and overflow indicators are influenced as with the addition instruction (PA) . This instruction changes the other indicators depending on the result loaded into the R register. The new value is retained and can be checked until another instruction finds the indicator again.

Addition to memory and jump - (PASY. The memory location specified by the effective address is increased by one. Carry and overflow indicators are not affected. With this instruction, the other indicators are changed depending on the value stored in the effective address. The new value persists and can be checked until another instruction changes the indicators. If the result is zero, the JAR is incremented by one before the next instruction is fetched. A .R field with the value zero denotes the IAR, one of Zero different R field an index register.

AND and OR to the mask - (PNM and POM): The format of FIG. 4 A applies with the exception of bits 8 to 14, which are set to zero, and bit 15, which is the "C" bit. The content of the. Bits 0 to 3 of the register indicated by the field are ANDed (C = 0, PNM) or ORed (C - I, POM) with the content of the interrupt mask register and the result is placed in the mask register. An R field with the value zero denotes the accumulator, an R field other than zero denotes an index register. The source register is not changed. Carry over and overflow indicators are not affected, this instruction does not change the other indicators. A one bit in the mask allows an interruption.

Execute I / O - (PIIO): This instruction follows that in FIG. 8, in which bits 11 to 15 must be zero. The operation of this instruction and the bitfcld definitions are described later. In general, however, the condition code is set in the carry and overflow indicators. Carry is bit 0 and overflow is bit 1. The other indicators are not affected by a P / .O direct write instruction. However, the indicators are changed to mark the data. which are loaded into the specified register by the Γ /, Ό direct read instruction.

Step output - (PLEX): Bits 0 to 4 define the OP code. bits 5 to 15 are nail.

When this instruction is executed, the processor will run out of the current stage: if If there are no other interruptions pending, the Processor in the ... state. Carry over and overflow indicators are not changed. This instruction does not affect the other indicators.

Stop - (PSTP): This instruction comprises 16 bits, where bits 0 to 4 are the unique OP code, but bits 5 to 15 are zero

ίο have to. This instruction is only carried out if the system is prepared from the outside as if a console switch is on. Otherwise solves this instruction does not exclude an operation. When the instruction is executed, the processor runs in the stop state at the end of this instruction. No indicators are affected by this instruction.

VIII - I / O operations

so The format for I / O instructions of the processor is shown in FIG. 8 shown. The different fields have the following meanings:

Bits G through 4 - These bits represent the code field for the processor opcode. The value

■ 15 00001 corresponds to PIIO. The R-VeXa is used to designate the register in the processor that is affected by this I / O instruction. A Λ-field with the value zero denotes the accumulator.

In the case of direct read / write commands, the .R field specifies the register which is used as the source target field for the data to be transmitted. When preparing I / O , the R field specifies the register which is the source for the preparation information and which is transferred to the interrupt source. The R field is not used when I / O is stopped. If the interrupt is set, the Ä field specifies the register which contains the interrupt data record which is transmitted to the direct control channel.

FUN - The function field indicates the type of I / O command to be executed. This command can be direct write, direct read, prepare I / O , stop I / O or set interrupt. Invalid functions result in a program test interruption in the processor.

MOD - The modification field is only used with the direct read or direct write commands. It is used by the addressed unit to determine the operation to be carried out.

The unit address field (device addr) contains 6 bits of binary coded address information. It denotes a point, a group or a unit within a module. The module address field is a binary-coded, 6-bit image with which the module addressed by the P / O instruction is selected. The condition code indicates to the program. whether the E, A operation indicated by the P / O instruction was carried out successfully or not and, if this is not the case, the reason for the failure.

Condition codes are generated in the following order for an I / O operation:

1. Condition code 3 - not connected,

2. Condition code 2 · - Occupancy or sub

break pending,

3. Condition Code 1 - Errors and

4. Condition code 0 - successful.

Direct writing - This command provides the parameters required to transfer 16 data bits from the specified register in the processor to the addressed unit. The modify field indicates the operation to be performed on the unit. If the operation was successfully completed or initiated, condition code 0 is set. If an error is detected, condition code 1 is set and the status is stored in the unit status word (DSW). When the unit is occupied. or is in an ongoing interruption state, condition code 2 is set. When the unit is not connected, condition code 3 is set.

Direct reading - The command supplies the necessary parameters for the transmission of 16 data bits from the addressed unit into the specified processor register. The modifier field specifies the Unit to perform. Condition codes are set in the same way as for the direct writing command described above.

I / O preparation (Fig. 4 c) - The command is executed in exactly the same way as the write command described above. The parameters given to the unit by the command are used by it to determine whether an interruption is permitted and at what level and with what divergence. The function taken over by this command allows a quick dynamic assignment and modification of the interrupt priorities as well as the code to which they belong. I / O preparation allows programs to perform this assignment function while other programs are running. Previously, this function was built into machine parts, and technical steps are required to change it. The operation of the system must be stopped while the change is being made. I / O preparation is an additional facility that further enhances the interrupt mechanism of the present invention as embodied in the IBM System 7. The modification field is zero and the 16-bit data byte that is transmitted has the following meaning:

LYL - Four bits (bits 0-3) indicating the priority interrupt level assigned to the interrupt source. Since it is assumed that the processor described here only supports four priority levels (0 to 3), only bit positions 2 and 3 of this field are used, ie the direct control channel ignores bits 0 and 1, which must be zero.

DISP - Four bits (bits 4 through 7) indicating one of 16 unique shifts for each interrupt level. The processor uses this field to locate the associated branch address in order to refer to the pre-stored service routine. Bits 8-14 are zero.

/ - The / bit (bit 15) takes over the interrupt control via the interrupt level (ie a per unit mask). A one bit allows an interruption. An interrupt source controlled by the I / O preparation function must not request an interrupt if its / bit is at zero. If a command causing an interruption is sent to an interrupt source whose / bit is set to NuI! condition code 1 is set and a command rejection is stored in the DSW (or in the CSW, if the device is in the control module). The command is not executed.

If the preparation I / O operation is successful, condition code 0 is set. If an error is detected, condition code 1 is set and the status is stored in the DSW (or CSW). If the addressed interrupt source is busy or an interrupt status is pending, condition code 2 is set. If the addressed module is not connected, condition code 3 is set. The preparation information stored in an interruption source is only reset when the system is reset.

Stop I / O - This command resets the addressed I / O module. The stop I / O command with a module address of 0 triggers a program check

ao interruption in the processor. Probe-based output points and preparation fields are not reset. Other controls, the status and ongoing interruptions are postponed. If the module is present, it is deferred and condition code 0 is set. If the module is not connected, condition code 3 is set. No other condition code occurs. If a unit has an interrupt pending in the processor interrupt buffer, the stop I / O command does not reset that interrupt. Hence, an interrupt from a source that has been deferred can actually be presented to the processor.

Set Interrupt - This command is issued by the processor and provides the information required to set a priority interrupt on the processor or an attention interrupt on another CPU. The module address field must indicate the control module. If the module address field is nonzero, an interrupt check is generated. The specified register must contain data in a format in which bits 0 to 3 indicate the level and bit 15 is a ".4" bit. The / 1 bit directs the interrupt to the processor or the other CPU. Bits 4 to 14 are reserved and must be zero.

If the A bit is equal to zero, the LKL field

5 "has the same meaning as in the I / O prepare command, and the interrupt is passed to the processor. The LFL field is sent to the direct control channel. If the direct control channel successfully enters this interrupt into the interrupt buffer mechanism, condition code 2 is set. If the required level has already set a program, condition code 2 is set, condition codes 1 and 3 are not used in this case.This form of the lower interrupt setting command is used for program distribution in the processor.

When the / 1 bit is equal to one, the break is routed to the other CPU. In this case service is requested from another processor with the interrupt setting command. The foreign connection generates an interrupt for the foreign unit and the corresponding connection status bit is set to attention. If that

Attention bit is activated successfully, becomes the condition code 0 set. If the attention bit is already set, condition code 2 is set. if the foreign unit is not available or does not exist in the syiitem configuration, the condition code 3 set. In this case of the interrupt setting command, condition code 1 is not set.

IX - Priority Interrupts ^!

As already mentioned in the introduction, the process by which the real-line system generates the Handles priority interrupts, which are vital to its eventual success. There are many for the priority interrupt mechanism of the data processing system described Points listed below:

A. I / O preparation: The operation of this command has already been described in Section VIII, so its contribution to the interrupt mechanism consists in the creation of the dynamic assignment and modification of levels and sub-levels for interrupt sources and in that the manipulation of pure unit masks is made possible.

B. The interrupt set command also described in Section VIII allows program control the distribution of tasks or subroutines at prescribed levels. So stand the same priority arrangements for externally generated interrupts and the program itself are available. This ensures a high degree of flexibility in the distribution of new tasks.

C. The embodiment includes a multi-level anticipatory priority interruption system. The stages assumed for this description are numbered 0, 1, 2 and 3. The smaller the number of levels, the higher the priority. If the processor is not working at one of these levels, it is in a wait state. An interrupt mask register IMR (see Fig. 3) is provided in the system with a bit position for each of the four interrupt levels (see description of PNN, POM, PSLM in Section VII). The content of this mask register can be manipulated by programs. A ones bit in a given stage position in the mask register allows an interrupt at that stage. A zero bit prevents the interruption. Thus the program has the ability to control interruptions on a level basis. In addition, a summary mask bit is provided in the IMR, which can also be manipulated by the program and prevents all interruptions when set to zero. A one-bit in this summary mask bit position permits the interruptions, which in turn are activated by the mask register. The algorithm used to determine the priority allows the current stage to be interrupted by a stage which has a higher priority, provided that this new stage is switched on by the summary mask bit and the mask register. So if z. For example, if level 2 is operating, it can be interrupted by level 1 or level 0, but not by level 3 or a new interruption at level 2. The routine running at a given level is terminated if not by higher ones Interruption levels is canceled. A routine is completed when the programmer issues the level exit instruction (see Section VII). When this instruction occurs, the processor determines if lower levels are pending, and if not, it goes to the wait country and waits for new ones Interruptions. When a lower level routine is executed and aborted by a higher level routine, its status is recorded in the system, and when the higher level routine is completed the system returns to the lower level at the breakpoint and then runs on the lower level to completion if no new interruptions occur.

D. 16 sub-levels are designated for each of the four levels. These are numbered from zero to F. There are no relative priority inevitable differences between the sub-stages a ^r given stage. The sub-level information is used to designate the original source of interruption for the machine parts in order to be able to establish the correct machine-supported connection to the operating routine (see the following section on automatic sub-level branching).

E. Interrupt Presentation: The direct control channel (see particularly Figs. 1 and 6) contains the Interrupt presentation mechanism. There is an interrupt buffer register for each of the four stages and an interrupt request lock is provided. All priority breaks have to run through this buffer. When a source of interruption such as B. the unit shown in Fig. 7, wishes to issue an interrupt request, takes it with the direct control channel either directly or via the internal interface of FIG. 7 connection and shares theirs with the channel Interruption level with. If the buffer corresponding to this level is already full, the accepts Channel the level information and request additional information from the unit, which will then be included in the Buffer is set. At this time the buffer becomes full and the interrupt request latch corresponding to that buffer becomes full is set. The information held in the buffer consists of the sub-level, the unit address and the module address and a summary status bit, which is described later.

If the buffer for the respective stage is already full at the time of a request, the Requirement stacked. The interrupting source is locked by setting its stack lock (see F i g. 7) advised that she must maintain her interruption condition until she is instructor receives to present this again via the direct Kanalsteuerunj. The one renewal of the present tion of the stacked interrupt request for a given level accompanying signal becomes auto automatically delivered through the direct control channel if the buffer for the relevant stage during dei Acceptance of the respective interruption by the processor becomes empty. The four interruption requests Locking bars (shown in Fig. 6) belonging to the four buffers form a group of the three Bolt groups, which the priority interruption me control the mechanism in the system. Interruptions set by the program and another pro Incoming interrupts from the processor are handled in a similar way. For put on by the program!

609 512/25

However, interruption is one shown in FIG. 6 provided interrupt block pre-buffer for the case that the buffer for the selected level is already full. This ensures that at least an interruption set by the program occurs at the prescribed level after the delivery an interruption setting command. The processor examines the four interrupt request bars that are sent from the direct control channel before the end of each instruction and while waiting continually. The current interrupt state of the processor is in a second group held in place by four bars, which are shown in FIG. 6 are shown as the running step bars. Just one of these

Bolt for level X and the current step bolt set.

F. Status rescue. Certain parts of a central processor can be recognized by the program, which works in this processor. These parts are called the program addressable parts. Typically consist of the registers that the program can manipulate or use, and conditions, that the program can create or check. One of the most important registers is the instructions through which the program has already run, and generally becomes the instruction address register called. Other parts of the processor cannot be addressed by the program and contain

At a given point in time, Rieeel can set 15 special work registers from machine elements If none of the latches is set, the program is, however, to be used

- - ■ - - · "· 'has no access. Such registers are available to the computing

and logic unit available and a large number of

g gg g

number of control and clock devices. When a

bi d W d

the system is waiting. The running level bars do not indicate which level of the processor

actually works at any given point in time. _ ,,., _- ■ ", a

Incoming interruption requests were previously the person

which is generated by the processor with the summary instruction address register through machine parts

Mask bit with the individual level mask in the mask. The program must then contain the content of all

kcnrcgister and with the value of the current level - it can address registers and conditions

bars compared. When the interruption is due to save. It then has to load its own values

the masking devices is switched on and 25 and continue to the end, where the interrupted

they have a higher priority than the current level, where values have to be restored. These

then the priority level control logic causes a study and restoring of the program

switch to the new level at the end of the addressable section of the central unit

at the end of the instruction or immediately if there is a considerable loss of time, which is one of the

System is waiting. The third mentioned 30 components in a total interruption is

The group of four bars consists of those shown in FIG. 6 avoided by the present invention

process-locking-in process shown. They will show the stages.

on which the processor is either currently working. The solution to this problem by the present invention or which is based on the execution of an invention consists in the parts of the central processing unit which can be aborted by the program adrest break with higher priority in machine items. To z. B. to prevent stage 2 from duplicating the ments; therefore for each interrupt level 2 are interrupted, no new request is accepted for an accumulator, seven index registers, the level for which the process input, an instruction address register and an indicator set latch are already set. intended. If the processor accepts a new interruption in the form of a simple changeover to level X , the volume on the corresponding bank of AT level locks is switched on by the Profende and the program addressable Data. As a result, a very zeß-on locking for the .Y stage is switched off. Fast status changeover on the system possible At this point in time, the request bar is in the and a high degree of integrity insofar as the direct control channel for the Z level is deferred 45 status information is saved and emptied by machine parts and the buffer. This condition is restored to all and a program is notified of interrupt sources that are not dependent on the other at the ΛΓ level to stack its own, and then to restore and save the first interrupt status, which accepts the source Interrupt buffer can be placed while an interrupt is being received. At the same time, this operation is not only the status and the system loads it, but the login with the heading "Interface also introduces the new status that affects the multiplexers" from Patrick and Rick ard running interruption relates. This status is written. Other requests at the same level are automatically made available to the routines, ar again forming a stack. If the processor operating at level X which is interrupted and working with a higher priority 55 saves the time-consuming request for the status of level, then the process ons becomes the I / O units. The unit address and the lock are left on, but the current level module address of the lower level is switched to the battery and the execution is loaded on the mulator of the main level, which reproduces the sub-new higher level. When this execution break has been allowed and the S bit is terminated, the processor scans the process-on-bar 60 to load the transfer indicator. The S bit is off and determines that the process-on-latch of the one-bit summary status stage X is set and thus indicates that the stage X pointer, which is shown in the in FIG. 7 has already been canceled, but the execution of monitoring of all device status indicators has already started. If there are more interruptions that are stored in the status register. If dai missing with higher priority, the processor takes the 65 S-bit is at zero, the interruption on eini work at the level X at the point is returned to, where it was broken off at normal Endbedinung at the Unterbrechungseinhei, and supplies it to the Fully traced back. No further status information is endune. At this point the process inputs are required and the unit directly stands for a.

new instruction available. If the 5-bit was at one, then there is an error or exception condition occurred and the program must then get a precise status description by adding requests a status presentation from the unit. The 5-bit can last through 400 nanoseconds Instruction are checked and contributes to the rapid response of the system by giving the possibility in the general case creates the requirement of the status and its subsequent analysis by this one Replace instruction to determine that a normal end condition has occurred.

G. Automatic sub-stage branching. The entire organizational processes associated with the interrupt switchover can be further reduced by automatic branching on the lower level. From the in F i g. 5 shows the processor memory allocation diagram, that the OS-OB hexadecimal point contains table references for the start instruction address tables (SIA tables) for each of the four levels. The content of each of these fixed addresses points to a table with start instruction addresses for the various sub-CT level values within the level. The sub-level can therefore be viewed as an offset value added to the base provided by the contents of the fixed part. If an interrupt occurs at level X, lower level Y , the processor addresses one of the four fixed locations which correspond to level X when handling this interrupt. It adds the value Y to this address and addresses the corresponding combination of level and sub-level in the associated SIA list in the level table. The data obtained from this memory access are stored in the instruction address register and form the address of the first instruction in the instruction routine for level A 'sub-level Y. Here again, a machine function takes the place (! Er J'rograrnmanalyse and ensures that the interruption is processed quickly, which means that the The abbreviation OlA in Fig. 5 means old instruction addressc.

The combination of several registers per interrupt level, the intended designation of the interrupt qucllc, of the summary status and the automatic sub-level branching allow a Status change within 800 nanoseconds between the end of the interruption of the instruction and at the beginning of the interruption for instruction. The defined position in the memory for interruption purposes is described in more detail below.

As already mentioned, the memory addresses are referred to in hexadecimal notation. The addresses 2 to 7 are in the in Fi g. 5 not assigned, but positions 0 and 1 are reserved for the ncuc start instruction. A forced branch is taken to this address after act machine part of the initial program load IPL expired i-.t. The positions OS, O9, OA and OB contain the notes for the start instruction address on levels 0 to 3. These notes are the base addresses of the level shift tables. The first word of every stage shift table is the program check of the old instruction address for this stage PROGΟΙΑ. The remaining 16 words are the start installation addresses for level X shift O to level X shift F. The table only needs to be as long as required by the cct assignment of shifts. The storage locations OD to OF accordingly contain the program check of the start instruction address PROGSIA. the power thermal warning start instruction address PWKF ₁ SY /! and the machine test start instruction address MCKSIA. These addresses are called class vectors and ίο are the addresses of the first instruction in the corresponding routine. Positions 10 and 11 are the old power / thermal warning instruction address PWRFIOA and the old machine test instruction address MCKlOA.

X - class breaks

In addition to the four priority interrupt levels, there are three required interrupts in the processor. These are: program check, machine

Extra test and performance / thermal warning. These interruptions cannot be turned off. A memory location is provided in each interrupt stage for storing the IAR in the event of a program interrupt check. Therefore, program test interruptions can occur and be serviced at any stage. Since machine testing and performance thermal warning interrupts are conditions that can occur throughout the machine, successive interrupts in either of these two classes are treated recursively.

If a class break is made, all priority levels are automatically switched off by the machine and must be switched on again at the request of the program. The interrupt mask is not changed and the priority levels are reactivated by the program issuing the POM or P.VM instruction. If a class interruption occurs, the rescue of registers with the exception of the IAR is a matter of de; Program. If the program test is interrupted, the instruction is not executed and none of the internal registers addressable by the program de; Processor changed.

As a result of a program test interruption, the address of the instruction which caused the error is stored in the old instruction address for program test of this level (e.g. in PROG IOA level 0) and the program test start instruction address is loaded into the IAR and execution commenced. A program check is carried out in the event of invalid PP code functions unc modification values, invalid shift number values unc if the appropriate memory size is

call or operand access is exceeded.

When a machine test interrupt occurs, the instruction address saved is the address the instruction that was being executed when the interruption occurred. A machine test triti in case of register or memory parity errors on and be; Machine errors in the processor's controls the channel or the interface.

In the event of a power thermal warning interruption, the saved instruction address is the address the next instruction. Performance / thermal alarm interrupts are only allowed between instructions. The condition occurs when or when the primary electrical power begins to fail

an overheating condition occurs in the system. Sufficient advance notice of these conditions is provided, so that the system can be switched off.

XI - working method ^;

The in F i g. 1 shown general system configuration of a data acquisition and process control system according to the inventive idea is to react with a minimum loss of time to requests made by the user units which are connected to the I / O modules. These ElA modules are connected to a direct control channel via a common interface for the purpose of exchanging data between the processor and the memory. The memory in the processor module can either be addressed by an exchange between this memory and the memory of another processor via a third-party connection, or it can be connected to other data processing systems via a communication adapter {ACCA), via which the exchange is then similar to the E / A modules are handled on an interrupt basis. Interval timers are contained separately in the processor module in order to be able to perform their timer functions independently and to be able to free the processor of the program load for this function. The intended operating station (operator station) allows the user to connect to the processor module via keyboard, punched tape or the like.

The memory of the processor module is either exchanged with another processor or initialized with the operator station by a monitoring program defining the tasks to be performed and the various memory allocations for stage and sub-stage processing as shown in FIG. 5 can be placed in memory. The processor module is then ready to initiate and begin controlling multiple tasks to be performed by the user units. These tasks can have various combinations of digital and analog data input and output include, although with the analog functions the conversion of the analog to digital 45 Signal level required for processing by the processor before sending these signals to the internal Interface can be given.

The processor can then begin the initialization of the various I / O modules by addressing the 50 respective I / O units as shown in FIGS causes various information relating to its ability to deliver interrupts to the processor to be stored. This includes a field which defines the interruption level that is to be used in the in FIGS. 2 and 7 is stored in the INT LEFEX register. The offset corresponding to the address of the respective processor subroutine, which the interrupt generated by the respective unit would service, is stored in the substage register. It also includes a bit mask on the unit that will or may not allow interrupts to occur. It is about 65 the / -bit, which is stored in the / -bit bar.

When a condition requiring an interruption occurs on the I / O unit, it sets its

Interrupt request interlock as shown in FIGS. 2 and 7, which enables the unit to attempt an I_W break processing at the interface multiplexer under the assumption that the / bit has previously been set for the unit and the stack bar ee clears. This interface multiplexer can be built as it is in the simultaneously registered! I Patent xer entitled "Schnittstellenmuitiple" by Patrick and Rickard described _s t This device has advantages, is provided rather than a "quick response to interruptions during a particular unit is gehinden fact dominate the interface. The direct control channel detects whether the interrupt buffer register belonging to the stage assigned to the service requesting unit is empty ^; If this is the case, the lower address level and the summary status associated with the unit are stored in its interrupt buffer register level and the interrupt request interlock associated with the buffer is set. The unit then competes effectively at the processor level for service as a function of its priority level.If the interrupt buffer register corresponding to the level of the requesting unit is already filled, then conversely the unit is instructed by the interface multiplexer to set its stack bar, reset its interrupt request bar and reset the interface to release. As soon as the interrupt buffer register belonging to the level in question is cleared by the processor, the interface multiplexer informs all units whose stacking bar is set so that they can then set their break request bar again and apply for service.In the processor, the priority level control logic reacts to the loading of the interrupt buffer register and setting the associated interrupt request bars only if the requested level is switched on and an interrupt at the same or a higher priority level is currently being processed. The bars of the current level and interrupts in progress line the priority level control logic of both the interrupt level being processed and the levels previously interrupted and request a return to the ultimate service for completion. As seen in Figure 6, the priority control logic is responsive to the issued interruption request with the highest level and actuates registers and sets conditions belonging to this level in order to exclude the other levels CP [/ controls are disconnected while only level 0 remains connected when a level 0 interrupt request is issued. In particular, FIG. 3 shows the components associated with the registers and condition circuits of each stage. When there is a level 0 interrupt, the / ICCO, all ^ Λ registers and level 0 IAR are operated while all other lower level registers are temporarily suspended. The ALU and the Speicner addressing function basically in a similar way to the conventional central unit ™ "c; c

■ Ti

However, a special mask register IMR has been included in the central unit, with which the masking of individual interrupt stages or all interrupt stages is possible. This means that the system of the invention effectively has six different criteria by which interrupts can be masked insofar as interrupts of certain levels by the IMR, and that all interrupts can be masked. Furthermore, these masking functions can be changed dynamically by program manipulation, which therefore provides a very high degree of flexibility for this system and enables a reaction to changing conditions. For example, if a particular I / O IPMENT is critical during short periods of time at a j _S given day, at other times can be ignored, however, but can use the I / O -Vorbereitungsinstruktion this unit on the day start a Unterbrechungsstufe0 distributive / -Bitriegel deleted permit. For these conditions, the unit can present any interrupt request. The programmer can then generate a prep I / O instruction at the beginning of the critical time period for that unit to only set the / bar, whereupon the unit will operate at its 0 interrupt priority. This / -bit bar can be deleted at the end of the critical time period, effectively suspending the operation of this unit. On the other hand, the EIA preparation instruction can initially be generated with a relatively low interrupt level, which is then simply changed to interrupt level 0 for the critical time.

The operating speed is further increased by the fact that various obligatory summations and unit status analyzes are avoided. These operations are left to the unit their summary siatus generator itself. The use of the 5-bit, which summarizes whether a Status request and analysis required allows the processor to handle this time load work around it when it is not necessary by simply using the S bit of data transfer through the buffer is added to the interrupt request.

The storage of the sub-level exposure on the unit, which is then transferred to the processor frees the processor from another time load since processing the interrupt allows the process to directly access the particular subroutine that the service request of the delivered unit.

In the example shown, the work area in the processor is a 16-bit logic circuit, the

an input to the ALU-Sammelleiiung supplies data are in the work area from a voi | four sources entered. This includes one of the accumulators that store logical and arithmetic operations, during long index loading operations an index register, the mask register during the OR-to-mask or AND-to-mask operations, and the mask register and the binary-coded current level during the level sensing and masking operations. The work area A RB-BEf] (Fig. 3) is also actuated by an interrupt level indication signal from the interrupt level and priority control circuits. The parity can be generated (PG) or checked (PC) at any desired point, although the in FIG. 3 positions shown are preferred for this process. Di (| specific data buses for data transmission between the processor and the A units has not been shown in detail since their Ar is Functioning generally known by the interface multiplexer Only the processing to Unterbrechungsverar and the sensing unit and the address for the preparation of E /. Parts belonging to A instruction were shown in FIG. 7 in particular

The processor can take on various background program functions by using the interruption pre-buffer of FIG. 6 sets so that the background effectively competes with the other units for an interruption level (|. This background gas processing naturally has a lower priority level. However, the programming can provide that only the background processing is carried out under certain critical circumstances. Di <| Original units, timers, operator station and communication adapter (ACCA) can also be set dynamically according to the units' £ 7 / f preparation operation.

According to the representation in FIG. 3, only the: / ΛΛ register can be increased by one. In order to avoid duplication or switching of circuits zi, which are normally affected by the address register operation, the choice of a priority level for operation can be accompanied by a transfer of the content of a corresponding recourse address register IARB into the IAR. Although a fallback register is generally not needed for level 0 (IARBO, since level 0 cannot be interrupted by another level, it can be used to record the content of the IAR de level 0 in the event of a class interruption! Another The IARBC \ could be used to record the instruction address that is currently being executed.

In addition 6 sheets of drawings

Claims (9)

Patent claims: 1. Electronic data processing system with externally connected data sources for the Execution of tasks on the basis of a priority level hierarchy, with a number of Control circuits, each of which is permanently assigned to a specific priority level, and with a device that responds to service request signals from the external data sources, characterized in that each control circuit carries out the operation of those known per se arithmetic and logical unit of the processor independent of the other control »Circuits can control that the service request signals the identifier of the priority level of the respective requesting external data sources is added so that only that control circuit is operated whose priority level corresponds to the ao pending service request signal with the highest priority corresponds, whereby the controller the said arithmetic and logical unit transferred to that control circuit which has the highest priority and that the presence of service request signals lower priority levels are not taken into account. 2. Data processing system according to claim 1, characterized in that each control circuit has an arrangement for keeping the signals theirs, the arithmetic and logical unit, associated operational status, the control device responding to the receipt of a service request signal with higher priority responds in that sb the operation interrupts the control circuit with a lower priority level at the point at which the storage arrangement has received enough data to allow a subsequent re-actuation of the interrupted control circuit and completion of the interrupted operation. 3. Data processing system according to claim 2, characterized in that the storage arrangements of the control circuits consist of a number of registers which are sufficient to form a central processing configuration together with the storage devices of the data processing system and the arithmetic and logic unit, and that in the control circuit actuating means contained for the operation of all the registers of a control circuit corresponding to the selected priority level, comprising, while on the other hand, the registers of all interrupted control circuits caused to such data aul v preserve / indicating their status in the interrupt. 4. Data processing system according to claim 2, characterized in that for cooperation with several external data sources, which each generate service request signals and Have arrangements for the storage of priority level data, also the following facilities the following are provided: a device for the selection of an external data source, a device to transmit a priority level that sends a data signal to the selected external Data source that is stored in this data source defines an actuator that to a service request signal from an external data source with the receipt of a Addresses priority level that defines the signal from the relevant external data source as a function of the transmitted priority level data signal and for actuation the control circuit group that corresponds to the priority level thus defined. 5. Data processing system according to claim 2, characterized in that for cooperation with several external data sources, the following facilities are also provided: certain memory areas in the addressable memory for several separately addressable Subroutines, a facility for selecting an external data source, facilities for the transfer of data showing a correlation between at least one subroutine address and perform the data memory of a selected data source, wherein the operating device Has circuits that respond to a service request signal from an external data source with the receipt of the transmitted Data from the memory of the external data source to cause the selected Control circuit do their work with the arithmetic and logical unit and the addressable Memory begins so that the stored subroutines are different from those of the corresponding data received from an external data source is addressed. 6. Data processing system according to claim 3, characterized in that furthermore the following is provided: a number of external data sources with memories, circuits to form a Output signal as a function of the contents of the memory and devices for the generation of service request signals, furthermore devices for the selection of external data sources and for the transmission of the priority level signals to said memories and finally Actuating devices which act on the output signals of the output signal forming device and said service request signals from responds to a relevant external data source with the actuation of the group that has a priority level which corresponds to the output signal forming device. 7. Data processing system according to claim 6, characterized in that the external data sources each have second memory that said addressable memory each have one Number of separately addressable subroutines in different memory locations have that further a device for the transmission of the data is provided, the at least one Subroutine addresses are assigned to the second memory of a selected external Data source, furthermore actuating means which respond to a request signal from an external data source responds with the receipt of the data transmitted from the second memory of the selected external data source in order to cause that the selected control memory with the arithmetic and logical unit and the address (ί sable memory cooperates, in accordance with the previously stored Subroutines addressed by the data received from the second memory of the corresponding external data source. 8. data processing system nsch claim 7, characterized in that each external data source ¹ consists of the following: a device for storing data which are indicadv for a number of conditions of an associated control unit, a logic device for monitoring this memory, which is always then an output signal is generated when the condition data adhere to the need for special attention from the external data source for said control unit and a device which, when service request signals from the associated external data source are present, is active in order to transmit the output signals of the logic device for monitoring to the control unit , whereby this control unit does not take into account the status exchange with the external data source, except when the output signal of the logic device for the monitoring is received. 9. Data processing system according to claim 8, characterized in that the following is also provided: a device for transmission of mask data to a selected external data source which has a third memory for the storage of the mask data and also has a control logic device, which is responsive to the state of the third memory to switch between actuation and non-actuation an external data source, depending on the service requirement the control unit, the output signal of the logic device for monitoring, the content of the second memory and the output signal of the educational institution.