Universal bidirectional grammar-driven engine for EDA file formats. One grammar drives parse + save for GDSII, LEF, DEF, Tcl.

T1C — Open-Source AI Accelerator Architecture. Like RISC-V did for CPUs, T1C does for AI chips. Fully open source, MIT Licensed.

Static timing analysis with signal integrity — WNS/TNS sign-off gate, SI/crosstalk + statistical OCV.

Combinational logic equivalence check: two gate-level netlists in, an equivalence verdict (with counter-example) out.

STA-driven buffer insertion: split high-fanout / over-transition nets to fix slew and timing.

STA-driven Vt swapping: trade threshold-voltage flavors (iso-footprint) to cut leakage while holding timing, or to close setup.

Headless GDS layout viewer: a GDS in, a layered SVG out — with optional violation overlay.

Public release home for the Vyges CLI — prebuilt binaries + curl/PowerShell installers (catalog, PDK, and Loom-engine installs). Homebrew tap: vyges/homebrew-tap.

Liberty characterization — SPICE + PDK models to .lib (NLDM + CCS), parallel-SPICE orchestration.

RC parasitic extraction — routed layout to SPEF; a calibrated sky130 deck tracks OpenRCX.

Layout geometry kernel: GDSII read/write, polygon boolean ops, and hierarchy flatten.

Power analysis: per-instance leakage + dynamic power and the activity map that closes char -> power -> em-ir.

Static glitch/hazard analysis: a gate-level netlist + Liberty in, reconvergent-fanout hazards out.

Power-integrity sign-off — power-distribution-network IR-drop + electromigration against a budget.

Layout-vs-schematic: SPICE netlist comparison with clear divergence diagnostics.

Structural clock-domain-crossing (CDC) checker: netlist + clocks in, crossings out.

Gate sizing — STA-driven drive-strength resize to close setup or recover area.

Steady-state on-chip thermal analysis + electro-thermal coupling — the thermal dual of vyges-em-ir

The shared design-data foundation for the Vyges Loom EDA suite — parse-once/query-many readers (Verilog, Liberty, SDC, SPEF) + an in-memory design database.

Design-rule check: a GDS layout + a rule deck in, geometry violations out.