CN1332334C - Multi-processor communication and its communication method - Google Patents

Abstract

The invention relates to a multiprocessor communication device and a communication method thereof, comprising a communication port and a crossover unit, the external memory interface of a processor is connected to the communication port, and data transmission is performed between the communication ports through the crossover unit The communication port includes an interrupt control unit and a communication port register group; the multiprocessor communication device and communication method realize full interconnection and direct real-time communication among different types of processors, and improve the versatility of the communication device. The communication device also has an interrupt generating device. Once other processors generate a communication request to the processor, an interrupt signal will be generated. The interrupt signal can meet the requirements of level trigger and edge trigger. When the same processor sends communication requests at the same time, the interrupt information will not be lost; the communication device uses a cross-switch unit to realize the information exchange of each communication port, and any processor in the system can communicate independently.

Description

A multiprocessor communication device and communication method thereof

technical field

The invention relates to a communication device and a communication method thereof, in particular to a communication device and a communication method applied to multiprocessor communication.

Background technique

Currently using multiprocessors for parallel processing is one of the best ways to improve system performance, and large embedded devices are often designed as multiprocessor systems. Multiprocessor systems are widely used in real-time application systems and other processing systems that require high computing power. These systems are becoming more and more complex. They may need to use multiple processors of the same type to form a parallel system, or they may need to use multiple processors of different types to form a system. All need to communicate, especially in real-time applications, more high-speed and reliable communication means are needed to effectively ensure the real-time performance of the system.

In order to solve the problem of interconnection and communication of multiple processors, in the prior art, the high-speed interface designed by the processor itself is used for interconnection communication, but the high-speed interface is a self-designed port of the processor itself, and these interfaces are usually only the internal standards of the enterprise , generally only communicate with processors of the same type. That is to say, the use of this high-speed interface for inter-multiprocessor interconnection communication is not universal, and most processors do not have this direct communication capability, which brings difficulties to the rapid communication between these processors.

Contents of the invention

The technical problem to be solved by the present invention is to provide a multiprocessor communication device and its communication method, improve its versatility, realize full interconnection between multiprocessors, and communicate information directly in real time and stably, avoiding the loss of communication information, Communication reliability is thereby improved.

In order to solve the above technical problems, the present invention provides a multiprocessor communication device, including a plurality of communication ports and a crossover unit, the external memory interface of each processor of the multiprocessor is connected to one of the plurality of communication ports, Data transmission is performed between the communication ports through the cross switch unit, the communication port includes an interrupt control unit and a communication port register group, and the communication port register group includes a communication setting register, a communication response register, a communication source register and a message register group, where:

The communication setting register is used to send communication requests to other communication ports;

The communication response register is used to send communication response signals to other communication ports;

The communication source register is used to indicate a communication source;

The message register group is used to store communication information from interrupt signal sources.

In the above solution, the cross-switch units are completely interconnected, and each communication is independent of each other, and the cross-switch units use a unified clock signal, which has nothing to do with the clock of the processor connected to the communication device.

In the above scheme, the communication port responds to communication in an interrupt mode and sends an interrupt signal, and the interrupt control unit receives the interrupt signal sent by the communication port to perform interrupt service processing; through the communication port register set, the processor The external memory interface directly controls the reading and writing of the communication port register set.

In the above solution, the interrupt control unit processes level-triggered interrupts and edge-triggered interrupts. When multiple ports send communication requests to the same port, that is, multiple processors send communication requests to the same processor, the interrupt control unit multiple times Send an interrupt request.

In the above scheme, the communication setting register is composed of a low bit and a high bit, the low bit is the communication object code, and the high bit is used to describe the communication information.

In the above solution, each bit of the communication response register and the communication source register represents a processor.

In the above solution, each of the message register groups corresponds to a processor.

In the above solution, the communication information has a software-defined communication code.

In the solution above, the communication port responds to communication in an inquiry manner, and the processor checks the communication request by directly accessing the communication source register set.

The present invention provides a multiprocessor communication method, which is applied in a multiprocessor system, comprising the following steps:

a) The source processor sends a communication request to the target processor through the communication device, and the communication request includes target information and communication information;

b) The communication device writes the communication information into the communication port corresponding to the target processor for storage, specifies the communication source in the communication port corresponding to the target processor, and simultaneously sends an interrupt signal to the target processor;

c) After the target processor receives the interrupt signal sent by the source processor, it enters the interrupt processing service, and judges that it is a communication request sent by the source processor;

d) The target processor reads the content of the stored communication information and judges the content;

e) The target processor performs corresponding processing according to the judgment result;

f) The target processor clears the interrupt sent by the source processor;

g) The target processor judges whether it needs to send a response message to the source processor? If yes, go to step a),

At this time, the positions of the source processor and the target processor are exchanged, if not, go to the next step;

h) The communication ends.

As can be seen from the above, the communication device and the communication method can realize the direct and real-time communication of full interconnection among different types of multiprocessors, and the communication device uses a crossover unit to realize the information exchange of each communication port. The communication can be carried out independently; the communication device can be connected with different types of processors, which improves the versatility.

In addition, there is an interrupt generating device in the communication device, and when multiple processors send communication requests to the same processor at the same time, the interrupt information will not be lost, thereby improving the reliability of communication.

Description of drawings

Fig. 1 is the structural block diagram of multiprocessor communication device of the embodiment of the present invention;

Fig. 2 is a composition diagram of a communication port in a multiprocessor communication device according to an embodiment of the present invention;

Fig. 3 is an interrupt control logic diagram in a communication port of a multiprocessor communication device according to an embodiment of the present invention;

Fig. 4a is a flow chart of the communication method of the multiprocessor communication device of the present invention;

FIG. 4b is a flowchart of a communication method of a multiprocessor communication device according to an embodiment of the present invention;

Detailed ways

To communicate between multiprocessors, it is necessary to send and receive communication information through a communication device, which requires reading and writing external memory. The external memory interface of the processor can be divided into 2 types, synchronous interface and asynchronous interface. Synchronous interface is used to connect with synchronous memory (such as SDRAM, DDR RAM, etc.), and asynchronous interface is used to connect with asynchronous memory (such as DRAM, FLASH, ROM, etc.). Asynchronous memory interface generally does not need clock control. In various processors Widely present, the present invention uses an asynchronous memory interface.

The asynchronous memory interface usually consists of three parts: address signal, control signal, and data bus. The address bus width and data bus width are defined according to the address mapping and data access conditions of a specific processor.

The technical solution of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a structural block diagram of a multiprocessor communication device. As shown in the figure, the multiprocessor communication device includes a communication port and a crossover unit. The communication device connecting N processing machines has N communication ports, the first communication port 11, the second communication port 12, the third communication port 13, the fourth communication port 14, the fifth communication port 15, and the Nth communication port 16 , data exchange is performed between the above communication ports through the cross switch unit 17 . The structure of each port is the same, each port has an interrupt signal, which is used to send interrupt control to the processor; in addition, each port has a set of registers, called the communication port register set, and the external memory interface of the processor directly controls these Read and write of the communication port register set.

The communication ports of the multiprocessor communication device in the embodiment of the present invention will be described in detail below with reference to FIG. 2 .

FIG. 2 is a structural diagram of the communication port in the communication device. As shown in the figure, the communication port includes a set of communication port registers 26 and an interrupt control unit 25 for inter-processor communication. The communication port register group is composed of a communication setting register 21 , a communication response register 22 , a communication source register 23 and a message register group 24 . in:

The communication setting register 21 is used to send communication requests to other processors, and it is made up of two parts, and the low order is (N-1) position communication target code, and high (M) position is used for describing communication information, and communication information is automatically generated by the software. The defined communication code, the processors can use these communication information to carry out high-speed small amount of information transmission to meet the requirements of quick response, and these communication information can also be used to explain the meaning of this communication. That is to say, the processors can not only complete the operation of sending interrupts to each other, but also directly transmit data, and the specific amount of data can be customized according to needs.

The communication response register 22 is used to send communication response signals to other processors, and it is made up of (N-1) bits, and each represents a processor in the system except this processor, and writing 1 means to clear the corresponding processing Machine interrupt signal.

The communication source register 23 is used to indicate which processors are communication sources, and it is made up of (N-1) bits, and each bit corresponds to a processor, and if a certain bit value is 1, it means that the corresponding processor is processing The computer has sent a communication request, and 0 means there is no communication request.

The (N-1) message register group 24 stores communication messages from interrupt signal sources. The width of each register is M bits, and each register corresponds to a processor for storing communication information sent by other processors.

As shown in Figure 1 and Figure 2, if a processor writes to the communication setting register in its port register group, the cross-switch unit will write the communication object code content in the communication setting register to the communication setting register. The communication information is written into the message register of the corresponding processor whose value is 1 in the communication target code, and the corresponding position of the communication source register of the target processor is set to 1. The cross-switch units 17 in the communication device are fully interconnected, and each communication is independent of each other. The cross switch unit 17 uses a unified clock signal, which has nothing to do with the clocks of the processors. The processors in the system can work at the same frequency or at different frequencies, and these processors can also be of different types.

In the communication port register group, each processor that needs to communicate has a corresponding register to control, it can accept communication requests sent from any one or more processors, and can also send communications to any one or more processors Request information, and the processors in the system communicate fully interconnectedly. When the source processor sends a communication request to the target processor, the corresponding bit of the communication source register of the target processor will be set to 1, and at the same time, the interrupt control unit will send an interrupt signal to the target processor, and the interrupt signal will be sent to the logic control unit of the communication port. 25 for interrupt signal processing, and then the destination processor reads information from the source processor.

The processing of the interrupt signal by the interrupt control unit in the communication port will be described in detail below in conjunction with FIG. 3 .

FIG. 3 is a schematic diagram of the interrupt control unit of the communication port in the communication device. As shown in the figure, after the system is reset, the output terminal (B) of the counting logic is 1. When any one or several positions of the communication source register are 0 (change from 1 to 0), the input terminal (A terminal) of the counting logic has a high level for one cycle, and after the counting logic detects the high level of the input A, it will The counter is reset to 0, and the output B is set to 0, and the counter starts counting by 1. When the counter is full, it stops counting, and the output B is set to 1, which forces any one or several positions of the communication source register to be 1. , the interrupt signal has a low level.

Interrupting the control unit avoids loss of communication information. If processor A in Figure 3 sends an interrupt request, an interrupt signal will be generated at this time. When the target processor reads its communication source register, processor B will send another communication request. At this time, the processor will not be able to process this immediately. ask. After the target processor finishes processing the communication request of processor A, it will write 0 to the A position of its communication source register, and the interrupt control logic will give the interrupt of processor B again after a certain delay (controlled by the counter). .

Due to the function of the counting logic, the interrupt signal generated by the interrupt control unit can meet the requirements of edge-triggered interrupt and level-triggered interrupt of the processor at the same time. The interrupt control unit ensures that when multiple processors send communication requests to the same processor at the same time, the interrupt control unit can send interrupt requests multiple times without losing interrupt information.

In addition to using interrupts to respond to communication, the processor can also directly access its communication source registers to determine whether there are communication requests from other processors. This method is called query mode. Using this communication method, the processor does not need to External interrupt interface. Since each interrupt source has a corresponding message register, when multiple processors send communication requests to the same processor, the communication information is also independent of each other, and the target processor can also identify each communication request.

As shown in Figure 4a, a multiprocessor communication method applied in a multiprocessor system comprises the following steps:

a) The source processor sends a communication request to the target processor through the communication device, and the communication request includes target information and communication information;

b) The communication device writes the communication information into the communication port corresponding to the target processor for preservation, specifies the communication source in the communication port corresponding to the target processor, and sends an interrupt signal to the target processor simultaneously;

c) After the target processor receives the interrupt signal sent by the source processor, it enters the interrupt processing service, and judges that it is a communication request sent by the source processor;

d) The target processor reads the content of the stored communication information and judges the content;

e) The target processor performs corresponding processing according to the judgment result;

f) The target processor clears the interrupt sent by the source processor;

g) The target processor judges whether it needs to send a response message to the source processor? If yes, go to step a),

At this time, the positions of the source processor and the target processor are exchanged, if not, go to the next step;

h) The communication ends.

The communication method of the multiprocessor is described below with a communication example. There are 4 processors in the system, 3 bits are used to represent the communication target code in the communication setup register, and 4 bits are used to describe the communication information. The corresponding relationship between the communication object code accessed by each processor and each bit of the communication source register is as follows:

bit 1 Bit 2 Bit 3 Processor 1 Processor 2 Processor 3 Processor 4 Processor 2 Processor 1 Processor 3 Processor 4 Processor 3 Processor 1 Processor 2 Processor 4 Processor 4 Processor 1 Processor 2 Processor 3

As shown in Figure 4b, when the first processor sends communication information (0001) to the third processor, the communication device completes the communication process including the following steps:

Step 100, the first processor writes (0001010) into its communication setting register, wherein "1" in the last three digits 010 represents sending communication information 0001 to the processor corresponding to the bit, that is, the first processor sends the communication information to the third processor The computer sends a communication request 0001;

Step 110, the crossover unit writes the communication information (0001) into the first message register of the third processor according to the target information content (010) in the communication setting register, and sends an interrupt signal to the third processor, and at the same time connects The corresponding position of the communication source register in the third communication port of the third processor is 1, i.e. 100 (compare the table above);

Step 120, the third processor receives the interrupt signal sent by the first processing unit, enters the interrupt processing service, performs interrupt signal processing in the interrupt control unit connected to the communication port of the third processor, and reads the value of its communication source register 100. It is possible to determine the communication request sent by the first processor;

Step 130, the third processor reads the information of the first message register in the communication port, and judges the communication content;

Step 140, the third processor performs corresponding processing;

Step 150, the third processor writes 000 to the communication response register in the communication port to clear the interrupt sent from the first processor.

Step 160, after the third processor finishes processing the communication information, if it needs to send communication feedback information to the first processor, it can send information to the first processor according to the above method.

In the above communication process, if the third processor successively receives the interrupt signals sent by the first processor and the second processor, it can be known from the description of the function of the interrupt control unit that the communication port connected to the third processor After the interrupt control unit has processed the interrupt signal sent by the first processor, the interrupt control unit gives the interrupt signal of the second processor again after a certain delay, and then processes it. The processing of the interrupt signal is the same as step 130, except that the value of the read communication source register is different.

In the case of multi-processors (more than 3) interconnected, the above-mentioned communication process steps and interrupt processing process are also applicable, except that the length of the communication setting register, communication response register, and communication source register changes with the number of processors. The value of varies with the communication object according to the regulations of each register.

Claims (10)

1. A multiprocessor communication device, comprising a crossover unit, characterized in that it also includes a plurality of communication ports, and the external memory interface of each processor of the multiprocessor is connected to one of the plurality of communication ports, Data transmission is performed between the communication ports through the cross switch unit, the communication port includes an interrupt control unit and a communication port register group, and the communication port register group includes a communication setting register, a communication response register, a communication source register and a message register group, where: The communication setting register is used to send communication requests to other communication ports; The communication response register is used to send communication response signals to other communication ports; The communication source register is used to indicate a communication source; The message register group is used to store communication information from interrupt signal sources. 2. The multiprocessor communication device according to claim 1, wherein the crossover unit is completely interconnected, and each communication is independent of each other, and the crossover unit uses a unified clock signal to connect with the communication device The clock of the processor is irrelevant. 3. The multiprocessor communication device according to claim 1, wherein the communication port responds to communication in an interrupt mode, and the interrupt control unit sends an interrupt signal; through the communication port register group, the processor's The external memory interface directly controls the reading and writing of the communication port register set. 4. The multiprocessor communication device according to claim 1, wherein the interrupt control unit processes level-triggered interrupts and edge-triggered interrupts, and when multiple ports send a communication request to the same port, that is, multiple processors send a communication request to the same port. The same processor sends a communication request, and the interrupt control unit can send the interrupt request multiple times. 5. The multiprocessor communication device according to claim 1, wherein the communication setting register is composed of low bits and high bits, the low bits are communication object codes, and the high bits are used to describe communication information. 6. The multiprocessor communication device according to claim 1, wherein each bit of said communication response register and said communication source register represents a processor. 7. The multiprocessor communication device of claim 1, wherein each of said message register groups corresponds to a processor. 8. The multiprocessor communication device according to claim 5, wherein said communication information carries a software-defined communication code. 9. The multiprocessor communication device according to claim 1 or 2, wherein the communication port responds to the communication in a query mode, and directly accesses the communication source register group to check the communication request. 10. A method for processor communication using the multiprocessor communication device described in claim 1, comprising the following steps: a) The source processor sends a communication request to the target processor through the communication device, and the communication request includes target information and communication information; b) The communication device writes the communication information into the communication port corresponding to the target processor for storage, specifies the communication source in the communication port corresponding to the target processor, and simultaneously sends an interrupt signal to the target processor; c) After the target processor receives the interrupt signal sent by the source processor, it enters the interrupt processing service, and judges that it is a communication request sent by the source processor; d) The target processor reads the content of the stored communication information and judges the content; e) The target processor performs corresponding processing according to the judgment result; f) The target processor clears the interrupt sent by the source processor; g) The target processor judges whether it needs to send a response message to the source processor, if yes, go to step a), at this time, the source processor and the target processor are exchanged, if not, execute the next step; h) The communication ends.