JPH11145789A - Low power consumption register circuit - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To provide a low power consumption circuit that performs low power consumption and efficient data processing. SOLUTION: The power consumption of a register circuit which takes in and outputs data in synchronization with a clock signal is reduced. The input and output of the register are compared and monitored by the comparison circuit.
A judgment result signal is output. The logical sum of the input judgment control signal and the judgment result signal is obtained by an OR gate, and the output is latched by the D flip-flop in synchronization with the inverted signal of the clock signal input to the register. The logical product of the output and the clock signal is taken by an AND gate, and the output signal is used as a clock signal to be supplied to the register.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low power consumption register circuit, and more particularly, to a data processing circuit for performing signal processing or the like, which is inputted to each register by a change in data inputted to each register. The present invention relates to a low power consumption register circuit that reduces power consumption by controlling a clock.

[0002]

2. Description of the Related Art An integrated circuit formed as an LSI includes various functional circuit blocks such as a flip-flop circuit for taking in a data input signal supplied thereto in synchronization with a clock signal. And LSI
When a synchronous circuit is used in designing an integrated circuit, a functional block such as a flip-flop circuit is configured to always receive a clock signal.

However, as the scale of the LSI increases and the operating speed increases, a large number of flip-flop circuits are formed into LSIs, and even if it is not necessary to change the values of the flip-flop circuits, the clock can be increased. Even if the signal is always input and the contents of the flip-flop circuit itself are not changed, there is a problem that the clock signal changes and consumes unnecessary power, and it is necessary to suppress the unnecessary change of the clock signal. There is.

As one means for solving the above problems, Japanese Patent Laid-Open No. 7-99434 (low-power consumption circuit)
In a low power consumption circuit having a functional circuit block that captures a data input signal supplied to itself in synchronization with a clock signal, the necessity of the functional block for performing the capture operation of the data input signal is considered. First circuit means for judging, and output of a clock signal is permitted when a signal indicating true is output from the first circuit means;
A second circuit for prohibiting the output of the clock signal when a signal indicating no is output, and a clock signal output from the second circuit is supplied as a clock signal for the functional circuit block. Low power consumption circuits have been proposed.

FIG. 16 is a diagram for explaining a low power consumption circuit disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 7-99434. FIG. 16 shows partial functional blocks of an LSI. , launches the signals l ₁ is input, the start signal l ₁ is received by the first-stage circuit portion 6 and the flip-flop 1 is supplied at all times clock, the first-stage circuit portion 6 of the entire circuit shown in FIG. 16 Activate the operation, flip
Flop 1 ignites flip flop 2 through OR gate 4.

The flip-flop 2 is connected to an AND gate 3
And feeds back the signal l ₄ from the output terminal of the flip-flop 2 by constructed self-holding operation circuit by the OR gate 4 performs the self-holding, feedback if the output signal l ₅ of NOR gate 8 '1' The loop is broken and reset. The NOR gate 8 is a circuit for determining whether or not the subsequent-stage circuit unit 7 is operating, that is, whether or not it is necessary to take in the data input signal and change the value held by the NOR circuit unit 7. 7 shows the results of summarizing signals indicating that signals need to be captured.

Registers 9 (register A), 11 (register B), 13 (register C) and 15 (register D)
The latch timing is controlled by a signal generated from the first-stage circuit unit 6 or the second-stage circuit unit 7 as necessary. The logic circuits 10 (logic circuit A), 12 (logic circuit B), and 14 (logic circuit C) include registers (A) 9, (B) 11, (C) 13, (D) 15
This is a circuit that logically connects the inputs (1) and (2) with any circuit configuration.

FIG. 17 is a timing chart for explaining the operation of FIG. 16, where l ₂ is an input clock signal, l ₁ is a start signal, l ₃ is an output signal of flip-flop 1, and l ₄ is a flip-flop 2 output signal, _{l 5} is a NOR gate 8
The output signal l ₆ is the output signal of the AND gate 5 (ie,
Internal clock). The internal clock ₁₆ output from the AND gate 5 functions as a gated clock, and is supplied to the post-stage circuit unit 7 and the registers 11 and 13.

[0009] The clock supplied to the portion in which the portion performing the operation closed to the functional block (that is, the logic for determining the change of the flip-flop including the register) exists only in the functional block is in the operation of the functional block. Only for a certain time, a normal clock is applied to a flip-flop whose change is determined by an input signal from another functional block. A storage element in a functional block, that is, a flip-flop, a register, a memory, or the like, only needs to have a clock as timing information that causes the operation to change, and does not need a clock in a non-operation. It is.

As described above, in the case of the D-type flip-flop, a circuit composed of three-input and equivalent elements is connected to the clock input signal, and the circuit inputs "1" and "0" in synchronization with the clock input. In order to repeat the operation,
Power is consumed in this part. In a functional block having a low operation frequency, particularly in a CMOS circuit, it is possible to reduce power consumption by not providing an unnecessary clock. When the reset signal ₁₇ is used, it is necessary to turn on the flip-flop 2 so that the reset operation is completed normally.

[0011]

As described above, according to the invention described in Japanese Patent Application Laid-Open No. H07-99434, by suppressing unnecessary clock signal changes, that is, when the same data is input, the register ( B) 11 and register (C)
By stopping the clock supplied to the power supply 13, the power consumption is reduced. However, when considering the data input / output of the four-stage pipeline configuration circuit, the register output originally desired for each stage in the four-stage pipeline configuration circuit is as shown in FIG.
As shown in the lower part of FIG. 8 (the clock control method according to the present invention), the outputs of “register A”, “register B”, “register C”, and “register D” must have a one-to-one correspondence. (In FIG. 18, hatched portions indicate the same data).

However, in the configuration described in Japanese Patent Application Laid-Open No. 7-99434, as shown in the upper part of FIG. 18 (a clock control method according to the prior art), the pipeline is disturbed, and "register A" and "register B" are disturbed. , "Register C", and "register D" have a one-to-one correspondence with the input, that is, "register B" and "register C" receive the same clock signal. Since the power is supplied, the output of the final stage “register D” cannot respond to the input.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. Control of an LSI clock signal according to a change in a flip-flop circuit (the clock signal also changes in accordance with a change in data) is performed. The purpose of the present invention is to provide a low power consumption circuit that performs low power consumption and efficient data processing.

[0014]

According to a first aspect of the present invention, there is provided a synchronous register circuit for fetching and outputting data in synchronization with a clock signal. A data judging section for outputting a signal, an OR gate for ORing the inputted judgment control signal and the judgment result signal, and synchronizing an output of the OR gate with an inverted signal of a clock signal inputted to the register. A D flip-flop to be latched; and an AND gate for performing an AND operation between the output of the D flip-flop and the supplied clock signal, and using the output signal of the AND gate as a clock signal supplied to the register It is characterized by the following.

According to a second aspect of the present invention, there is provided a low power consumption circuit in a synchronous register circuit for fetching and outputting data in synchronization with a clock signal, and more particularly, in a pipelined circuit, the circuit according to the first aspect includes a basic circuit. By connecting the basic circuits, a clock signal is supplied only to a group of registers to be operated without causing disturbance of the pipeline.

According to a third aspect of the present invention, in the first or second aspect of the present invention, the data determination unit not only compares and monitors the input / output of an arbitrary register, but also performs the input / output of another register input simultaneously. Is characterized in that the clock signal supplied to each register is controlled by comparing and monitoring at the same time.

According to a fourth aspect of the present invention, there is provided a synchronous register circuit including a plurality of stages of registers for taking in and outputting data in synchronization with a clock signal.
Data match / mismatch detection means for detecting match / mismatch between input data and output data of the first stage register and outputting a detection signal, and in accordance with a match detection signal from the detection means,
Clock signal supply control means for inhibiting the supply of the clock signal to the first register and permitting the supply of the clock signal to the first register in response to the mismatch detection signal from the detection means; Provided in response to
A latch circuit for storing the coincidence / mismatch detection signal transmitted in synchronization with data transmission between each stage register, and a coincidence detection signal from the latch circuit provided for the second and subsequent stage registers. , The supply of the clock signal to the second and subsequent stage registers is prohibited, and the supply of the clock signal to the second and subsequent stage registers is permitted according to the mismatch detection signal from the latch circuit. And a clock signal supply control means.

[0018]

FIG. 1 is a diagram showing the basic components of a power consumption control circuit according to the present invention.
1, the data comparison unit 21, the D flip-flop 22, the OR gate 23, and the A
The ND gate 24 is provided. That is, a data comparison circuit 21 for comparing input data and output data of a target register 30, a D flip-flop 22, AND
It has a very simple circuit configuration composed of one gate 24 and one OR gate 23. The basic circuit 20 is arranged in each register along the flow of data processing. With this basic circuit configuration, each register controls the clock signal, and information on the control of the clock signal performed by each register is transmitted along the data processing flow, thereby suppressing pipeline disturbance. I do.

In FIG. 1, first, it is determined whether or not to operate the data comparison unit 21 based on the value of the determination result signal generated in the previous stage. When the determination result signal is “1”, the data comparison unit 21 is stopped. If the determination result signal is “0”, the data comparison unit 21 is operated. When the data comparison unit 21 determines to perform data comparison based on the determination result signal, the data comparison unit 21 compares and monitors data input to the register 30 and data output from the register 30. The data comparing unit 21 generates “1” as a determination result signal when the data and the data value match, and generates “0” as the determination result signal when the data does not match the data.

FIG. 2 shows the basic circuit shown in FIG.
In the time chart for explaining the operation when the data of D2 is continuous for two cycles, the judgment result signal generated in the previous stage and the judgment result signal are input to an OR gate 23, and the judgment result signal is output. The decision result signal is a D flip-flop 22 at the falling edge of the clock signal.
It is taken in. The determination result signal is output as a determination result signal at the fall of the next cycle of the clock signal. The determination result signal is ANDed with the next basic circuit 20.
Output to the gate 24. A clock signal is input to the AND gate 24 in addition to the determination result signal. The AND gate 24 outputs the clock signal as a clock signal of the register 30.

With the basic circuit 20 of the present invention, the clock signal input to the register 30 is masked except for the necessary clock pulse, so that the register 30 and the clock pulse connected thereto do not perform unnecessary operations, and Since clock control information is transmitted to the next-stage register as a determination result signal, "register A", "register B", and "register C" as shown in the clock control method according to the prior art shown in the upper part of FIG. It is possible to perform fine control of the clock signal without causing a pipeline disturbance in which the outputs of the "register D" and the "register D" cannot correspond one-to-one.

First Embodiment FIG. 3 is a diagram for explaining a first embodiment (a pipeline configuration when data flows in one direction) of a low power consumption register circuit to which the present invention is applied, and FIG. Is a diagram showing a modified example 1 (pipeline configuration with loop processing) of a low power consumption register circuit to which the basic circuits 20A, 20B, and 20C according to the present invention are applied.
The basic circuits 20A, 20B, and 20C of the present invention installed in the registers 30A, 30B, and 30C for data processing, and installed in the registers 30A, 30B, and 30C, respectively, determine the determination result signals A, B and C are connected. The control of the clock signal input to the register of each stage is performed by comparing and determining the input data and the data in the previous cycle.

FIG. 5 shows an example of a timing chart when data processing proceeds in one direction shown in FIG.
As shown in (1), the control of the clock signal is determined by the content of data in each stage, and the information of the clock control is transmitted along the flow of data processing, so that the disturbance of the pipeline Will not occur. The AND gate 50 shown in FIG. 3 outputs “H” only when both the determination result signal from the basic circuit 20A and the determination result signal from another module are “H”. The AND gate 60 of FIG. 4 is similar to the AND gate 50 of FIG.
"H" is output only when both the determination result signal from 0A and the determination result signal B from the basic circuit 20B are "H".

The low power consumption register circuit to which the present invention is applied transmits clock control information between registers, and determines control of a clock signal by input / output of data in each register. The present invention can also be applied to a case where data is input / output from / to another circuit in the middle of the process, or a case where a loop process for obtaining a cumulative sum as shown in FIG. 4 is present.

Embodiment 2 FIG. 6 is a diagram for explaining an embodiment (pipeline configuration having a branch: arithmetic unit) to which the present invention is applied when a plurality of data flows into one data processing system. And FIG.
Shows a circuit example of a multiplier to which the present invention is applied, and FIG.
1 shows a general circuit configuration. In such a case, the data decision unit in the basic circuit has the following functions. 6 and 7, if "register", register A input data 31 = register A output data 32 and register B input data 33 = register B output data 34, the comparison signal (judgment result signal) A35 is Outputs “1”.

If not "register", register A input data 31 = register B output data 34 (replace input of A with output of B) and register B input data 33 = register A output data 32 ( If the input of B is replaced by the output of A, then the comparison signal A35 outputs "1".

If not (if not, if not, if not), the comparison signal A35 outputs "0".

As described above, by providing the data comparator with the functions described above, unnecessary power consumption in the multiplier can be suppressed. Further, by assuming each module as one register and arranging the circuit of the present invention in a tree-like manner in each module unit, it is possible to perform clock control in module units and clock control in register units, which is more efficient. Power consumption can be suppressed.

FIG. 8 is a diagram showing an example of a configuration in which a register is added. FIG. 8 shows 4-bit serial data a.
1 to d are temporarily latched, and an example of a register composed of D flip-flops 100 to 103 outputting a to d in synchronization with the rise of the system clock is shown.

FIG. 9 is a diagram showing a detailed example of the embodiment shown in FIG. 3. The register has the configuration shown in FIG.
As the data comparing section, the one having the configuration shown in FIG. 10 was used. The data comparison unit is configured to output data a input to the register 100 and data a output from the register 100
EXNO that outputs H (high) when
R circuit 104; EXNOR circuit 105 that outputs H when data b input to register 101 and data b output from register 101 match; data c input to register 102 and output from register 102 EXNOR circuit 106 that outputs H when data c matches data EX, and EXNOR circuit 10 that outputs H when data d input to register 103 and data d output from register 103 match.
7 and the outputs of the respective EXNOR circuits 104 to 107 are input, and the respective EXNOR circuits 104 to 107 are input.
AND circuit 1 that outputs H only when all outputs are H
08, the judgment result signal from the preceding basic circuit and AND
NOR that receives the output of the circuit 108 and outputs H when any of the determination result signals from the preceding basic circuit or the output of the AND circuit 108 is H or both are H
And a circuit 109.

The basic circuit 20A includes a data comparing section 21A
And a NOR circuit 110 to which a determination result signal from the preceding basic circuit and an output from the data comparing unit 21A are input.
And a D flip-flop 111 for temporarily latching the output of the NOR circuit 110 and outputting the same in synchronization with the fall of the system clock, and an AND circuit 112 to which a signal obtained by inverting the output of the D flip-flop 111 and the system clock are input. It is composed of The output of the D flip-flop 111 is output as a determination result signal A1, and this determination result signal A1 and the determination result signals from other modules are input to the AND circuit 113. The output from the AND circuit 113 is input to the next-stage basic circuit 20B as the determination result signal A.

The basic circuit 20B temporarily latches the judgment result signal A from the basic circuit 20A and outputs the D flip-flop 11 in synchronization with the fall of the system clock.
4 and an AND circuit 115 to which a signal obtained by inverting the output of the D flip-flop 114 and a system clock are input. The output of D flip-flop 114 is output as determination result signal B. The basic circuit 20C temporarily latches the determination result signal B from the basic circuit 20B, outputs the D flip-flop 116 in synchronization with the fall of the system clock, a signal obtained by inverting the output of the D flip-flop 116, and the system clock. Where is input
And a D circuit 117. D flip-flop 11
6 is output as the determination result signal C.

In the case of the configuration example shown in FIG. 9, the basic circuit is:
Although the data comparison unit 21A is provided only in the basic circuit 20A (the data comparison unit is not provided in the basic circuits 20B and 20C), the data comparison unit is provided in each of the basic circuits 20B and 20C. Is also good. FIG. 11 is a diagram showing a configuration example in that case. In this case, the basic circuits 20B and 20C also have data comparison units 21B and 21C, and these comparison units 21B and 21C correspond to the basic circuit 20A shown in FIG. Operates exactly the same as the data comparison unit 21A.

FIG. 12 is a diagram showing a detailed example of the embodiment shown in FIG. 4. The configuration of the registers 30A, 30B and 30C and the configuration of the basic circuits 20A, 20B and 20C are shown in FIG. The configuration is the same as that described above. In this case, as in the example of FIG. 11, the basic circuit 20B and the basic circuit 2
A data comparison unit may be provided for each of 0C. FIG.
Shows a configuration example in that case.

In the embodiments shown in FIGS. 3 and 4, a logic circuit is provided between the registers, but FIGS. 14 and 15 show examples of the configuration in which no logic circuit is provided between the registers. The example shown in FIG. 14 has a configuration in which only the basic circuit 20A has a data comparison unit 21A, and the other basic circuits 20B to 20D do not have a data comparison unit. The example shown in FIG. Circuit 2
All of the data comparison units 21A to 21D have the data comparison units 21A to 21D. The logic circuit is an AND circuit, a NOR circuit,
Circuit, an AND circuit, an OR circuit, an inverter, and the like.

[0036]

As is apparent from the above description, according to the present invention, a basic circuit is installed in each register of the data processing module with respect to an existing circuit, and the basic circuit is connected along the flow of data processing. By doing so, a circuit that operates with the minimum required power consumption can be created. Further, since there is no need to worry about the disturbance of the pipeline, there is no need to adjust the processing time of the entire circuit.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic circuit configuration of the present invention.

FIG. 2 is a timing chart for explaining the operation of the basic circuit of the present invention.

FIG. 3 is a diagram illustrating a first embodiment (a pipeline configuration in a case where data flows in one direction) of the present invention;

FIG. 4 is a diagram illustrating a modified example 1 (pipeline configuration with loop processing) of the present invention.

FIG. 5 is a diagram showing a pipeline control timing chart according to the present invention.

FIG. 6 is a diagram showing a second embodiment (a pipeline configuration with a branch: (multiplier)) of the present invention.

FIG. 7 is a diagram illustrating an example of a data comparator circuit according to the second embodiment of the present invention;

FIG. 8 is a diagram illustrating a configuration example of a register.

FIG. 9 is a diagram showing a detailed circuit example of the embodiment shown in FIG. 3;

FIG. 10 is a diagram illustrating a detailed circuit example of a data comparison unit.

FIG. 11 is a circuit diagram showing a modified example of FIG. 9;

FIG. 12 is a diagram showing a detailed circuit example of the embodiment shown in FIG. 4;

FIG. 13 is a circuit diagram showing a modified example of FIG.

FIG. 14 is an improved circuit diagram of the embodiment shown in FIGS. 3 and 4, showing an example in which a logic circuit is omitted from the embodiment shown in FIGS. 3 and 4;

FIG. 15 is a diagram showing a modified example of FIG.

FIG. 16 is a diagram for describing a configuration example of a register.

FIG. 17 is a diagram showing a detailed circuit example of the embodiment shown in FIG. 3;

FIG. 18 is a diagram illustrating a detailed circuit example of a data comparison unit.

[Explanation of symbols]

1, 2 ... flip-flop circuit, 3 ... AND circuit, 4
... OR circuit, 5 AND circuit, 6 initial circuit section, 7 subsequent circuit section, 8 NOR gate, 9, 11, 13, 15 register (A, B, C, D), 10, 12, 14,. Logic circuits (A, B, C), 20, 20A, 20B, 20C, 2
0D: Basic circuit, 21, 21A, 21B, 21C, 21
D: Data comparison unit, 22: D flip-flop, 23
... OR gate, 24 AND gate, 30, 30A, 3
0B, 30C, 30D ... register, 40A, 40B, 4
0C: logic circuit, 50, 60: AND circuit, 100-1
03 ... D flip prop, 104-107 ... EXNO
R circuit, 108 ... AND circuit, 109 ... NOR circuit.

Claims (4)

[Claims] In a synchronous register circuit for taking in and outputting data in synchronization with a clock signal, a data judgment unit for comparing and monitoring input data and output data of a register and outputting a judgment result signal is provided. An OR gate for calculating the logical sum of the judgment control signal and the judgment result signal;
A D flip-flop for latching an output of the R gate in synchronization with an inverted signal of a clock signal input to the register, and an AND gate for performing an AND operation between an output of the D flip-flop and the supplied clock signal Wherein the output signal of the AND gate is used as a clock signal supplied to the register. 2. A synchronous register circuit having a pipeline configuration for fetching and outputting data in synchronization with a clock signal, wherein the circuit of claim 1 is used as a basic circuit, and the basic circuits are connected to form a pipeline register. A low power consumption register circuit characterized in that a clock signal is supplied only to a register to be operated without causing disturbance. 3. The clock judging section not only compares and monitors input / output data of a predetermined register but also compares / monitors input / output data of another register which is input simultaneously, and supplies a clock to each register. 3. The low power consumption register circuit according to claim 1, wherein the signal is controlled. 4. A synchronous register circuit including a plurality of registers each of which takes in and outputs data in synchronization with a clock signal, wherein a match / mismatch between input data and output data of a first stage register is provided. And a data match / mismatch detection means for outputting a detection signal, and, in response to the match detection signal from the detection means, inhibiting the supply of a clock signal to the first stage register. Clock signal supply control means for permitting the supply of the clock signal to the first stage register, and provided in correspondence with each of the second and subsequent stage registers, and transmitted in synchronization with data transmission between each stage register. A latch circuit for storing the match / mismatch detection signal, and two stages corresponding to registers of the second and subsequent stages. Clock signal supply control means for prohibiting the supply of a clock signal to the first and second stage registers and permitting the supply of the clock signal to the second and subsequent stage registers in response to a mismatch detection signal from the latch circuit And a register circuit.