CN105846830B - Data processing equipment - Google Patents

Abstract

The present invention provides a data processing device, which comprises: m data processing modules for processing N _i data or operations in the ith cycle according to the calculation sequence; wherein And m<n, m, n and N _i are all positive integers, Through the multiplexing of m data processing modules in time, the processing of n data or operations is achieved, thereby reducing the consumption of hardware resources.

Description

data processing device

technical field

The present invention relates to the technical field of information theory and coding, and in particular, to a data processing device.

Background technique

With the rapid development of communication technology and the continuous improvement of information reliability requirements of various transmission methods, error control coding technology, as an important means of anti-interference technology, has shown more and more importance in the field of digital communication and digital transmission systems. effect.

Low-density parity check (LDPC) codes are a class of linear block codes whose decoding performance is close to the channel limit. Due to its excellent error correction performance, binary LDPC codes have been widely used in various communication, navigation and digital storage systems. Multi-ary LDPC codes have also become a good contender for error correction coding schemes in these systems in the future.

However, most of the encoders or decoders that implement LDPC codes in the prior art adopt a fully parallel structure. Taking an encoder with a fully parallel structure as an example, it is assumed that the data to be encoded is c=(c ₀ , c ₁ . _{...... _} The data processing module is used to calculate the product of c=(c ₀ , c ₁ . . . _ck-1 ) and a column in G _k×n , however, this fully parallel structure consumes a lot of hardware resources.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide a data processing apparatus, so as to achieve the purpose of reducing hardware resource consumption.

In a first aspect, an embodiment of the present invention provides a data processing apparatus, including: m data processing modules, configured to process N _i data or operations in the ith cycle according to the calculation sequence; wherein And m<n, m, n and Ni are all positive integers,

With reference to the first aspect, in a first possible implementation manner of the first aspect, the m data processing modules are specifically configured to: in the low density parity check LDPC encoding process, respectively calculate the data to be encoded c=(c ₀ , c ₁ . . . c _k-1 ) is multiplied by each column in the generator matrix G _k×n , where k represents the length of the data to be encoded, and n represents the number of columns of the generator matrix G _k×n ; Calculate c=(c ₀ , c ₁ . . . c _k-1 ) in the ith cycle and multiply by Ni columns in the generator matrix G _k×n , where the preceding cycles, the N _i =m, in the cycles, the N _i =nmodm,

With reference to the first aspect, in a second possible implementation manner of the first aspect, the data processing module includes: a first storage unit and a second storage unit; the data processing module is configured to convert the generator matrix G _k× Each column of _n is divided into P first data blocks, where p≥2; the first storage unit is used to store one of the first data blocks; the second storage unit is used to store the first data block The corresponding second data block of the data to be encoded; the m data processing modules are specifically used for: in the low-density parity check LDPC encoding process, according to the block result, in the i-th cycle to calculate N _i The second data block is multiplied by the corresponding N _i first data blocks, where the preceding cycles, the N _i =m, in the cycle to cycles, the N _i =nmodm,

With reference to the first aspect or the first possible implementation manner or the second possible implementation manner of the first aspect, in a third possible implementation manner of the first aspect, the method further includes: a first storage module, configured to store the generated matrix.

With reference to the third possible implementation manner of the first aspect, in a fourth possible implementation manner of the first aspect, the first storage module is specifically configured to: if the generator matrix is a sparse matrix, the first storage module The module only stores the non-zero elements of the generator matrix and the position coordinates corresponding to the non-zero elements; if the sub-matrix of the generator matrix is a circulant matrix, the first storage module only stores all the Non-zero elements, the position coordinates corresponding to one of the non-zero elements in one column, and the cyclic offset of the two adjacent columns.

With reference to the first aspect, in a fifth possible implementation manner of the first aspect, the method further includes: a second storage module, where the second storage module is configured to store a check matrix H _l×n ; a column of the check matrix Corresponding to variable nodes, the rows of the check matrix correspond to check nodes.

In a second aspect, an embodiment of the present invention provides a data processing apparatus, including: a second storage module, configured to store a check matrix H _l×n , where the columns of the check matrix correspond to variable nodes, and the columns of the check matrix correspond to variable nodes. Rows correspond to check nodes. The third storage module is used to store the data transferred between the variable node and the check node in the process of data processing. e first data processing modules for processing data on e check nodes; f second data processing modules for processing data on f variable nodes; where e<1, f <n, where e and f are both positive integers.

With reference to the second aspect, in a first possible implementation manner of the second aspect, if the parity check matrix is composed of a cyclic arrangement matrix and a zero matrix, then the third storage module performs a cyclic arrangement according to the structure of the cyclic arrangement matrix. Self-incrementing addressing.

An embodiment of the present invention provides a data processing apparatus, the apparatus includes: m data processing modules, configured to process N _i data or operations in the i-th cycle according to the calculation sequence; wherein And m<n, m, n and Ni are all positive integers, Through the multiplexing of m data processing modules in time, the processing of n data or operations is achieved, thereby reducing the consumption of hardware resources.

Description of drawings

In order to illustrate the embodiments of the present invention or the technical solutions in the prior art more clearly, the following will briefly introduce the accompanying drawings used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can also be obtained from these drawings without any creative effort.

1 is a schematic diagram of an encoder with a fully parallel structure provided by the prior art;

FIG. 2 is a schematic diagram of a data processing apparatus according to Embodiment 1 of the present invention;

3 is a schematic diagram of a data processing apparatus according to Embodiment 2 of the present invention;

4 is a schematic diagram of a data processing apparatus according to Embodiment 3 of the present invention;

5 is a schematic structural diagram of a data processing apparatus according to Embodiment 5 of the present invention;

6 is a schematic structural diagram of a data processing apparatus according to Embodiment 6 of the present invention;

7 is a schematic diagram of a Tanner provided in Embodiment 6 of the present invention;

FIG. 8 is a decoding model of an SPC code and a REP code according to Embodiment 6 of the present invention.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

In the LDPC encoding process, it is assumed that the data to be encoded is c=(c ₀ , c ₁ . . . c _k-1 ), the generator matrix is G _k×n , and the product of them is the final encoded sequence, so the encoder needs to Calculate the product of c=(c ₀ , c ₁ . . . c _k-1 ) and each column of G _k×n . FIG. 1 is a schematic diagram of an encoder with a fully parallel structure provided in the prior art, as shown in FIG. 1 . As shown, the encoder includes n data processing modules, each data processing module is used to calculate the product of c=(c ₀ , c ₁ . . . c _k-1 ) and a column in G _k×n , that is, each The data processing module outputs one codeword of a final coding sequence, so the n data processing modules will output all the codewords in one operation cycle. The encoder with full parallel structure will cause waste of hardware resources. In order to solve this technical problem, the present invention provides a data processing device.

Example 1

FIG. 2 is a schematic diagram of a data processing apparatus according to Embodiment 1 of the present invention. The data processing apparatus can be applied to a scenario of LDPC encoding or decoding, where the apparatus can be an LDPC encoder or an LDPC decoder, as shown in FIG. 2, the data processing apparatus includes: m data processing modules 201 for processing N _i data or operations in the ith cycle according to the calculation sequence; wherein And m<n, m, n and N _i are all positive integers,

Specifically, for example, since the calculation sequence of multiplying c=(c ₀ , c ₁ . . . c _{k -1} ) and G _k×n is: c=(c ₀ , c ₁ . ) are respectively multiplied by the first to nth columns of G _k×n . The data processing apparatus in this embodiment has m data processing modules 201, and m<n. Therefore, in the first cycle, it can be calculated separately c=(c ₀ , c ₁ . . . c _k-1 ) is multiplied by the first column to the m-th column of G _{k×n to} output m codewords, in this example, Ni in the first cycle is m. In the second cycle, c=(c ₀ , c ₁ ... c _k-1 ) and the m+1th to 2mth columns of G _k×n can be calculated respectively. In order to make full use of the existing the hardware resources, and make each data processing module 201 process one data or operation as much as possible in each cycle. Further, in the _ith cycle, Ni data or operations are processed, and the _Ni operations here can be understood as _Ni multiplication operations, and the _Ni data here can be understood as _Ni specific numbers, or it can be N _i vectors, matrices, etc. This embodiment of the present invention does not limit this.

Further, the data processing device further includes a storage module for storing the data to be encoded c=(c ₀ , c ₁ . . . c _k-1 ) of length k, and a generator matrix G for storing length k Memory modules for each column of _k×n . Since each column is multiplied by c=(c ₀ , c ₁ . . . _ck-1 ) in sequence, the memory module for storing each column can achieve the effect of multiplexing.

Furthermore, the data processing device also includes a multiplier and an adder, and k multipliers are used to complete the correspondence between each element of the data to be encoded c=(c ₀ ,c ₁ . . .c _k-1 ) and the generator matrix For element-wise multiplication, k-1 adders are used to calculate the sum of the above products, and a codeword can be generated by the action of the multiplier and the adder.

An embodiment of the present invention provides a data processing apparatus, wherein the apparatus includes: m data processing modules, configured to process N _i data or operations in the ith cycle according to the calculation sequence; wherein And m<n, m, n and N _i are all positive integers, Through the multiplexing of m data processing modules in time, the processing of n data or operations is achieved, thereby reducing the consumption of hardware resources.

Embodiment 2

3 is a schematic diagram of a data processing apparatus provided in Embodiment 2 of the present invention. The apparatus may specifically be an LDPC encoder, wherein the encoder includes m data processing modules, and the m data processing modules are specifically used for: In the low-density parity check _LDPC encoding process, the data to be encoded c ₌ (c ₀ , c ₁ . The length of the encoded data; n represents the number of columns of the generator matrix G _k×n , and c=(c ₀ , c ₁ . . . c _k-1 ) and the generator matrix G _k×n are calculated in the i-th cycle Multiply N _i columns, where the first cycles, the N _i =m, in the cycles, the N _i =nmodm,

Since the data processing apparatus includes m data processing modules, the parallelism of the data processing apparatus can be called m.

For example, assuming m=3, k=3, n=5, then in the low density parity check LDPC encoding process, the three data processing modules in the first cycle calculate c=(c ₀ , c ₁ , c ₂ ) is multiplied with the 1st, 2nd and 3rd columns in the generator matrix G _3×5 , and in the second cycle, the two data processing modules calculate c=(c ₀ ,c ₁ ,c respectively ₂ ) Multiply with the 4th and 5th columns in the generator matrix G _3×5 .

Further, the data processing device further includes a storage module for storing the data to be encoded c=(c ₀ , c ₁ . . . c _k-1 ) of length k, and a generator matrix G for storing length k Memory modules for each column of _k×n . Since each column is multiplied by c=(c ₀ , c ₁ . . . _ck-1 ) in sequence, the memory module for storing each column can achieve the effect of multiplexing.

Furthermore, the data processing device also includes a multiplier and an adder, and k multipliers are used to complete the correspondence between each element of the data to be encoded c=(c ₀ ,c ₁ . . .c _k-1 ) and the generator matrix For element-wise multiplication, k-1 adders are used to calculate the sum of the above products, and a codeword can be generated by the action of the multiplier and the adder.

An embodiment of the present invention provides a data processing device, the device includes m data processing modules, and the m data processing modules are specifically used for: in a low density parity check LDPC encoding process, respectively calculate the data to be encoded c= (c ₀ , c ₁ . . . c _k-1 ) are multiplied by each column in the generator matrix G _k×n , where k represents the length of the data to be encoded, and n represents the column of the generator matrix G _k×n number, calculated at the ith cycle c=(c ₀ , c ₁ . . . c _k-1 ) and multiplied by N _i columns in the generator matrix G _k×n , where the preceding cycles, the N _i =m, in the cycles, the N _i =nmodm, Thus, the time multiplexing of the data processing modules is realized, and further, the consumption of hardware resources is reduced.

Embodiment 3

FIG. 4 is a schematic diagram of a data processing apparatus according to Embodiment 3 of the present invention. On the basis of Embodiment 2, Embodiment 3 divides each column in the generator matrix G _k×n into blocks. Based on the idea of dividing, the embodiment The data processing module in the provided data processing device includes: a first storage unit 401 and a second storage unit 402; wherein, the data processing module is configured to divide each column of the generator matrix G _k×n into P first storage units data block; where p ≥ 2. As shown in FIG. 4 , the first storage unit 401 is used to store a first data block; the second storage unit 402 is used to store the second data block of the to-be-encoded data corresponding to the first data block; The first storage unit 401 stores a first data block with a length of d at this time, and the second storage unit 402 stores a second data block with a length of d at this time. Of course, the data processing module also includes a multiplier, an adder and an accumulator. , the m data processing modules are specifically used for: in the low density parity check LDPC encoding process, according to the block result, in the ith cycle, calculate the difference between the N _i second data blocks and the corresponding N _i first data blocks. multiplied by which precedes cycles, the N _i =m, in the cycle to cycles, the N _i =nmodm,

Specifically, the first storage unit 401 can be multiplexed with respect to each first data block, and the second storage unit 402 can also be multiplexed with respect to the second data block, that is, there is no need to open up redundant storage space, all the One first storage unit 401 may be used for the first data block in chronological order, and only one second storage unit 402 may be used for all second data blocks in chronological order.

For example: suppose m=3, k=3, n=5, P=2, that is, each column of the generator matrix G _3×5 is divided into 2 first data blocks, for each column, the order from top to bottom , the first element constitutes a first data block, and the second element and the third element constitute a first data block. Therefore, the generator matrix G _3×5 actually includes 10 first data blocks. The encoded data c=(c ₀ , c ₁ , c ₂ ) is also divided into 2 second data blocks, from left to right, the first element c ₀ constitutes a second data block, the second elements c ₁ and The third element c ₂ constitutes a second data block, then in the low density parity check LDPC encoding process, according to the calculation sequence, that is, in the first cycle, the three data processing modules respectively calculate c=(c ₀ , c ₁ , c ₂ ) is the product of the second data block formed by the first element and the first data block formed by the first element of the first column in the generator matrix G _3×5 , c=(c ₀ ,c ₁ ,c The product of the second data block formed by the first element of ₂ ) and the first data block formed by the first element of the second column in the generator matrix G _3×5 , c=(c ₀ , c ₁ , c ₂ ) The product of the second data block formed by the first element and the first data block formed by the first element of the third column in the generator matrix G _3×5 ; in the second cycle, the three data processing modules calculate c= The second data block composed of the second element and the third element of (c ₀ , c ₁ , c ₂ ) and the second data block composed of the second element and the third element of the first column in the generator matrix G _3×5 The product of a data block, the second data block formed by the second element and the third element of c=(c ₀ , c ₁ , c ₂ ) and the second element of the second column in the generator matrix G _3×5 The product of the first data block formed by the third element, the second data block formed by the second element and the third element of c=(c ₀ , c ₁ , c ₂ ) and the generator matrix G _3×5 The product of the first data block consisting of the second element and the third element of the third column, and the calculation results are respectively accumulated with the calculation results in the first cycle, and so on. Thereby realizing the multiplexing of data processing modules.

An embodiment of the present invention provides a data processing device, wherein a data processing module of the device includes: a first storage unit and a second storage unit; the data processing module is configured to divide each column of the generator matrix G _k×n into P the first data block; the first storage unit is used to store a first data block; the second storage unit is used to store the second data block of the data to be encoded corresponding to the first data block; m data processing modules, specifically Used for: in the low density parity check LDPC encoding process, according to the block result, in the i-th cycle, calculate the multiplication of Ni second data blocks and the corresponding Ni first data blocks, where the preceding cycles, the N _i =m, in the cycle to cycles, the N _i =nmodm, Thus, the utilization efficiency of the data processing module and the first storage unit and the second storage unit in the module is improved, and the computational complexity of each data processing module is reduced.

Embodiment 4

The fourth embodiment of the present invention provides a data processing device, wherein the device realizes the multiplexing of storage space based on the idea of obtaining the final coded sequence through the check matrix. Specifically, the specific method for obtaining the final coded sequence through the check matrix is as follows: suppose The data to be encoded is M=(m ₀ , m ₁ ...... m _k-1 ), the check matrix is H _l×n , and the check symbols are p ₁ , p ₂ ...... p _nk , then Assuming that the check matrix is H _l×n =(QI), where Q is the matrix of (nk)×k, corresponding to M, and I is the matrix of (nk)×(nk), corresponding to the redundant bits of the encoded data, when I is a quasi-bidiagonal matrix, that is, when the elements of I except the elements on the diagonal and the elements above or above the diagonal are all 0, the matrix is a quasi-bidiagonal matrix. based on It can be obtained that the first redundant bit p ₁ can be directly calculated from the elements in the data to be encoded, and the second redundant bit p ₂ can be calculated from the first redundant bit p ₁ and the elements in the data to be encoded. , and so on, p _nk can be jointly calculated by p _nk-1 and the elements in the data to be encoded. _Therefore , the ₍ M, _{p 1} , p ₂ ......p _nk ), read the non-zero elements from the storage module that stores the parity check matrix, multiply them, store them in the accumulator, and then store (M, (M,p ₁ ,p ₂ ......p corresponding to the second non-zero element in the first row of the parity check matrix) is read from the memory module of p ₁ ,p ₂ ......p _nk ) _nk ), read out the non-zero elements from the storage module storing the parity check matrix, then multiply them, and add the result to the result in the accumulator. And so on, until the first check digit is calculated, and the result in the accumulator is stored in the storage module storing (M, p ₁ , p ₂ ......p _nk ). Finally, clear the accumulator and repeat the above steps until all redundant bits are calculated. The above process realizes the multiplexing of storage space according to the sequence of computing time.

Embodiment 5

FIG. 5 is a schematic structural diagram of a data processing apparatus according to Embodiment 5 of the present invention. On the basis of Embodiment 1, Embodiment 2 and Embodiment 3, the data processing apparatus includes m data processing modules 501 except for , and also includes a first storage module 502, where the first storage module 502 is used to store the generator matrix.

Specifically, the first storage module 502 is specifically used for:

(1) If the generator matrix is a sparse matrix, the first storage module 502 only stores the non-zero elements of the generator matrix and the position coordinates corresponding to the non-zero elements.

Specifically, if the number of non-zero elements in the matrix is much smaller than the total number of matrix elements, the matrix is called a sparse matrix. Therefore, the first storage module 502 only stores the non-zero elements of the generated matrix and the position coordinates corresponding to the non-zero elements. . Further, when binary LDPC coding is adopted in the present invention, the non-zero elements in the generator matrix are only 1. Therefore, only the position coordinates corresponding to the non-zero elements 1 may be stored in the first storage module 502 .

(2) If the submatrix of the generator matrix is a circulant matrix, the first storage module 502 only stores all non-zero elements in the circulant matrix, and the position coordinates corresponding to one column of non-zero elements and the adjacent two Cyclic offset of the column.

Specifically, if the submatrix of the generator matrix is a cyclic matrix, the generator matrix is a quasi-cyclic matrix, such as a generator matrix where G _ij is a circulant matrix, (i=1,2...s; j=1,2...r). Based on the characteristics of the circulant matrix, the first storage module 502 only stores all the non-circular matrix in the circulant matrix. The zero element, the position coordinate corresponding to one of the non-zero elements in one column, and the cyclic offset of the two adjacent columns. For example: Circular matrix of q × q Then the first storage module 502 can only store q non-zero elements, and then store the position of the non-zero element g ₀ in the first column, and the cyclic offset 1 of the two adjacent columns, so that the non-zero elements of other columns can be passed through The positions and cyclic offsets of the non-zero elements in the first column are derived. Further, when binary LDPC coding is adopted in the present invention, the non-zero elements in the generator matrix are only 1. Therefore, the first storage module 502 may only store the position and cyclic offset corresponding to the non-zero element 1.

An embodiment of the present invention provides a data processing apparatus, the apparatus further includes a first storage module for storing the generator matrix. Wherein, if the generator matrix is a sparse matrix, the first storage module only stores the non-zero elements of the generator matrix and the position coordinates corresponding to the non-zero elements; if the sub-matrix of the generator matrix is a cyclic matrix, the first storage module only stores the cyclic matrix All non-zero elements in the matrix, the position coordinates corresponding to one column of non-zero elements, and the cyclic offsets of two adjacent columns, thereby realizing the multiplexing effect of the first storage module. Thus, the consumption of hardware resources is reduced.

Embodiment 6

6 is a schematic structural diagram of a data processing apparatus according to Embodiment 6 of the present invention. The data processing apparatus in this embodiment of the present invention may be a decoder, and the data processing apparatus includes a second storage module 601 for storing checksums In the matrix H _l×n , the columns of the check matrix correspond to variable nodes, and the rows of the check matrix correspond to check nodes. The third storage module 604 is used to store the data transferred between the variable node and the check node in the data processing process. e first data processing modules 602 are used to process the data on the e check nodes; f second data processing modules 603 are used to process the data on the f variable nodes; wherein, e<1 , f<n, where e and f are positive integers.

Specifically, the data processing apparatus provided by the embodiment of the present invention uses a belief propagation algorithm, which is based on the iterative decoding of the Tanner graph. 7 is a schematic diagram of a Tanner provided in Embodiment 6 of the present invention, wherein the columns of the check matrix correspond to variable nodes, and the rows of the check matrix correspond to check nodes, representing a check equation, the upper row is a check node, and the lower row is a variable Node, the line connecting the variable node and the check node corresponds to the element in the check matrix that is not 0, which is called an edge. From the Tanner diagram, an LDPC code can be regarded as an interleaved connection of a Single Parity Check (Single Parity Check, SPC) code and a Repeat (Repeat, REP) code, and FIG. 8 is the SPC provided by Embodiment 6 of the present invention Code and REP code decoding model, decoding is an iterative process of belief information passing between variable nodes and check nodes through edges. First, the confidence information received by the channel is passed to the variable nodes, and each variable node sends the updated confidence information to each check node connected to it. This is the work of the SPC decoding model. Each check node sends update information to the variable node connected to it through calculation, which is the work of the REP decoding model. The whole decoding process starts from the variable node and repeats continuously until all the verification equations are satisfied and the decoding is completed, or the decoding stops when the maximum number of iterations is reached.

In the decoding process, the transmission input and output ports between the first data processing module 602 and the second data processing module 603 are not directly connected, but are connected through the third storage module 604, so that only e first data can be realized The processing module 602 and the f second data processing modules 603 can process l data and n data respectively through multiple operations.

The specific working steps of the e first data processing modules 602 and the f second data processing modules 603 include:

(1) The f second data processing modules 603 read the channel data corresponding to the first f variable nodes, initialize them into the third storage module 604, and make a hard decision, and then each second data processing module 603 reads the next group channel data, until all channel data are initialized into the third storage module 604;

(2) The e first data processing modules 602 read the data transmitted by the second data processing module 603 to the first e check nodes from the third storage module 604, perform calculations and verify the check equation, and save the results to In the memory 604, then each first data processing module 602 reads the data received by the next group of first data processing modules 602 from the third storage module 604, until the data calculation on all check nodes is completed;

(3) If all the check equations are satisfied, stop iterative decoding, and output the decoding result, otherwise, perform the second data processing module 603 to continue the calculation. The f second data processing modules 603 read the data passed by the first data processing module 602 to the first f variable nodes from the third storage module 604 , perform calculations and make hard decisions, and save the results back to the third storage module 604 , then each second data processing module 603 reads the data received by the next group of variable nodes from the third storage module 604, until the calculation of all variable nodes is completed;

(4) Repeat this until all check equations are satisfied or the maximum number of iterations is reached, and then the decoding is stopped.

Further, in the check matrix of the LDPC code, each row or each column has more than one non-zero element, and the corresponding first data processing module 602 and the second data processing module 603 also have more than one input/output port. The g inputs required by a single data processing module can be divided into multiple inputs, and the calculation is started after each input, and the required intermediate results are stored in the memory, and finally the required operation results are obtained, so as to realize the time Reuse hardware resources.

Taking the first data processing module 602 as an example, when the first data processing module 602 has only three ports, set the input of the first data processing module 602 to be D ₀ , D ₁ , D ₂ , and the two-port arithmetic circuit can directly The output data is calculated from the data, and the calculation steps are as follows:

(1) Read in D ₀ and save it in a group of memories;

(2) Read in D ₁ , save it in another set of memory, and use the two-port arithmetic circuit to calculate save the result to the third bank of memory;

(3) Read in D ₂ and use the two-port arithmetic circuit to calculate Overwrite the result to the memory of the original record D ₀ ;

(4) Read in D ₂ again, and use the two-port arithmetic circuit to calculate Overwrite the result to the memory _of the original record D1.

Among them, the above It may be an operation rule in the binary LDPC encoding process, or may be an operation rule in the multi-ary LDPC encoding process. At this time, the first data processing module 602 only reads the data of one port at a time, and only three sets of memories are needed to store all intermediate results and final results in the whole calculation process; when the first data processing module 602 has four ports, it can be The fourth port is ignored first, and according to the three ports, the first data processing module 602 performs calculation, and the result is calculated by the first data processing module 602 Stored in three sets of memories, and then according to the three ports, the input and output of any port of the first data processing module 602 is calculated The result is stored in the fourth group of memory, and then the input of the fourth port is operated with the data in the first three groups of memories, and the data in these three groups of memories is updated to the result of the operation, then only four groups of memories are needed. , and perform seven calculations to obtain all the outputs of the first data processing module 602 with four ports, and so on, when calculating the output of the first data processing module 602 with N ports, the last port can be ignored first, Calculate according to the first data processing module 602 of the N-1 port, then calculate the sum of the input data of all ports of the N-1 port and save it in a new group of memory, and then compare the input of the last port with the previous N-1 group of memories The data in the operation is performed, and the calculation result is updated to the corresponding memory, so that only N groups of memory can be occupied, and (3+N)(N-2)/2 calculations are performed to complete the calculation of the output data of all ports.

Optionally, if the parity check matrix is composed of Circulant Permutation Matrices (CPM for short) and a zero matrix, the third storage module 604 performs cyclic auto-increment addressing according to the structure of the cyclic permutation matrix. The non-zero elements corresponding to all the edges in Figure 7 are in the CPM. Assuming that a CPM in H represents the connection between the check node and the variable node, the offset of the CPM is o, that is, the CPM is obtained by cyclically moving all the rows of the p×p identity matrix to the right by o positions. The check node CN ₁ is connected to the variable node VN _o+1 , CN _po is connected to VN _p , CN _p-o+1 is connected to VN ₁ , and CN _p is connected to VN _o . We call the edges connecting the p consecutive check nodes and p consecutive variable nodes as block edges.

Therefore, the information exchange between the variable node and the check node in the entire Tanner graph is carried out one by one block edge. When the p variable nodes are updated in the order of VN ₁ , VN ₂ ,..., VN _p , firstly store their update results to addresses A ₀ +1, A ₀ +2,...,A respectively ₀ +p storage unit; then when the p check nodes connected to the loop block are updated sequentially, VN ₁ , VN ₂ ,. .., the updated result of VN _p . It's just that the starting address should start from A ₀ +o+1. When the address is self-added to A ₀ +p, it will be self-added from A ₀ +1 to A ₀ +o, thus realizing the information transfer of the corresponding connection. Using the addressing mode of the block edge, only the starting addresses A ₀ and o of the address segment of the storage unit are recorded. When the variable node is updated, the address starts from A ₀ +1 and ends at A ₀ +p; when the check node is updated, the address starts from A ₀ +o+1, and the loop increases to A ₀ +o and ends. In this way, compared with the traditional addressing mode in which the decoder exchanges information, the storage complexity is reduced to p/2, and the addressing efficiency is greatly improved by adopting the cyclic self-incrementing address generation mode.

An embodiment of the present invention provides a data processing apparatus, including: a second storage module for storing a check matrix H _l×n , where the columns of the check matrix correspond to variable nodes, and the rows of the check matrix correspond to the check matrix test node. The third storage module is used to store the data transferred between the variable node and the check node in the process of data processing. e first data processing modules for processing data on e check nodes; f second data processing modules for processing data on f variable nodes; where e<1, f <n, where e and f are both positive integers. Thereby, the multiplexing of the data processing module, the second storage module and the third storage module is realized.

Those of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments may be completed by program instructions related to hardware. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the steps including the above method embodiments are executed; and the foregoing storage medium includes: ROM, RAM, magnetic disk or optical disk and other media that can store program codes.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features thereof can be equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the embodiments of the present invention. scope.

Claims (6)

1. A data processing device, characterized in that, comprising: m data processing modules for processing N _i data or operations in the ith cycle according to the calculation sequence; in And m<n, m, n and N _i are all positive integers, The data processing module includes: a first storage unit and a second storage unit; The data processing module is configured to divide each column of the generator matrix G _k×n into P first data blocks, where p≥2; The first storage unit is used to store one of the first data blocks; The second storage unit is configured to store the second data block of the data to be encoded corresponding to the first data block; The m data processing modules are specifically used for: in the low density parity check LDPC encoding process, according to the block result, in the ith cycle, calculate the N _i second data blocks and the corresponding N _i first data blocks block multiplication, where the preceding cycles, the N _i =m, in the cycle to cycles, the N _i =nmodm, 2. The device according to claim 1, wherein the m data processing modules are specifically used for: In the low density parity check _LDPC encoding process, the data to be encoded c ₌ (c ₀ ,c ₁ . The length of the data, n represents the number of columns of the generator matrix G _k×n ; Calculate c=(c ₀ , c ₁ . . . c _k-1 ) at the ith cycle and multiply N _i columns in the generator matrix G _k×n , where the preceding cycles, the N _i =m, in the cycles, the N _i =nmodm, 3 . The apparatus according to claim 1 , further comprising: a first storage module, configured to store the generator matrix. 4 . 4. The device according to claim 3, wherein the first storage module is specifically used for: If the generator matrix is a sparse matrix, the first storage module only stores the non-zero elements of the generator matrix and the position coordinates corresponding to the non-zero elements; If the submatrix of the generator matrix is a circulant matrix, the first storage module only stores all non-zero elements in the circulant matrix, the position coordinates corresponding to one column of non-zero elements, and the circular offset of two adjacent columns. shift. 5. A data processing device, characterized in that: comprising: a second storage module, configured to store a check matrix H _l×n , where the columns of the check matrix correspond to variable nodes, and the rows of the check matrix correspond to check nodes; a third storage module, configured to store the data transferred between the variable node and the check node during data processing; e first data processing modules for processing operations on the e check nodes; f second data processing modules for processing the operations on the f variable nodes; where e<l, f<n, where e and f are both positive integers. 6. The apparatus according to claim 5, wherein, if the check matrix is composed of a cyclic arrangement matrix and a zero matrix, then the third storage module cyclically increases search according to the structure of the cyclic arrangement matrix. site.