JPS6313215B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention comprises an instruction processing unit that decodes instructions, calculates operand addresses, reads operands, etc., a storage unit that stores operands, etc., and The present invention relates to an information processing device using a pipeline control method, which has an arithmetic unit that performs arithmetic operations on operands under instructions from microinstructions, and in which each of these units can operate in parallel.

[Technical background of the invention and its problems]

In general, in pipeline control type information processing devices, instructions (MOVE instructions) that read and write large amounts of data placed at consecutive addresses in main memory, and large amounts of data placed at addresses at regular intervals, are used. When processing vector arithmetic instructions for reading and writing, the contents of these processes are complex, so the operation of the instruction processing unit is stopped during such processing, and most of the processing is performed by microprograms. At this time, continuous operand addresses or operand addresses at regular intervals are generated by the arithmetic unit in the arithmetic unit. However, in such arithmetic processing means, since the arithmetic unit is required to calculate the operand address in addition to the original operand arithmetic processing, there is a problem in that the overall processing capacity is reduced.

Further, the instruction processing unit is provided with a circuit for calculating operand addresses as shown in FIG. 1, so that operand addresses can be specified at high speed. That is, instruction register 1
The contents specified in the OP code part are decoded by the decoder (DEC) 6, and the output is sent to the index register (XR) 2 or the base register (BR).
By controlling each output gate 11, 12 of 3, the operation target of the adder (ADD) 4 is controlled, so that the operation of generating the result of operand address calculation in the address register (AR) 5 can be achieved at high speed. I have to. Furthermore, a method is also conceivable in which the MOVE instruction or vector operation instruction is decoded by the decoder 6, and continuous or regular interval operand addresses are sequentially obtained under the output control of the decoder 6. However, in general, the instruction specifications of MOVE instructions and vector operation instructions are extremely complicated.
If these decoding and control were performed only within the instruction processing unit, there was a drawback that the amount of hardware would be large.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and is an information processing system that enables high-speed reading and writing of data placed at consecutive addresses or addresses at regular intervals in main memory in a computer that processes instructions using pipe control. The purpose is to provide equipment.

[Summary of the invention]

The present invention adds some circuits to the operand address calculation circuit in the instruction processing unit so that continuous operand addresses or operand addresses at regular intervals can be generated under microprogram control. This allows you to effectively use existing hardware to read and write large amounts of data located at consecutive addresses.
It can process MOVE instructions and vector instructions that handle large amounts of data at regular intervals at high speed.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. FIG. 2 is a block diagram showing the structure of an operand address calculation circuit within an instruction unit according to an embodiment of the present invention. In the figure, the same parts as in FIG. 1 are designated by the same reference numerals, and the explanation thereof will be omitted. Components with the same reference numerals as in FIG. 1 are as follows:
It is the basic part for calculating operand addresses when executing instruction processing using pipeline control. In the figure, 7 is an arithmetic unit (AU), and 8 is an increment register (ER) provided between the arithmetic unit 7 and the adder (ADD) 4. 21 and 22 are data selectors provided on the input side of the adder (ADD) 4, respectively, and select control signals 121, 22 output from the decoder (DEC) 6,
122, each output of the operand address register (AR) 5 and the increment register 8 can be selectively input to the adder 4. 23 is a data selector provided on the output side of the adder 4, which selectively transfers the output data of the arithmetic unit (AU) 7 to the operand address register 5.
It is possible to set it to

Here, the operation of one embodiment will be explained. A MOVE instruction or a vector operation instruction is executed by repeatedly reading a large amount of data stored in the main memory according to a certain rule, performing an operation, and then writing it again. For this reason,
It is necessary to sequentially find addresses in the main memory to be read and written at high speed. A read operation of an operand data group will be explained using a vector operation instruction as an example.

For the operands of a vector operation instruction, that is, the operation elements, an address interval (hereinafter referred to as an element interval) on the main memory is specified by an OP code of the instruction or auxiliary information of another instruction field. To read such a group of operand data sequentially,
It is necessary to find a value by sequentially adding this element interval to the initial address of the operand. The initial address value of the operand is normally determined by the address calculation circuit in the instruction processing unit shown in FIG. 2 under pipeline control, and is held in the operand address register 5. Alternatively, it is stored in the operand address register 5 by the arithmetic unit 7 after processing by another microprogram. At this time, under the control of the microinstruction, the data selector 23 selects the output of the adder 4 when the initial address is determined by the address calculation circuit shown in FIG. If required, the output data of the arithmetic unit 7 is selected. Next, the value of the element interval of the vector is stored in the increment register 8 as instructed by the microinstruction. Then, the data selector 2 is controlled by the selection control signal 121.
1 selects the output of the operand address register 5, and the selection control signal 122 selects the data selector 2.
2 selects the output of the increment register 8 and also fixes the state of the decoder 6 so that the output of the output gate 12 is inhibited by the control signal 112. Thereafter, by selecting the output of the adder 4 with the data selector 23, each time the fetch clock of the operand address register 5 is generated, the element interval in the increment register 8 is added to the operand address in the operand address register 5. will be added. With one microinstruction, (1), control the fetch clock of operand address register 5,
(2), Control of reading and writing of operands (operation instructions),
(3) By simultaneously controlling the arithmetic unit (operation instructions) and repeating this microinstruction, vector data can be processed at high speed.

Furthermore, in the case of a MOVE instruction, if the data width that can be read and written in one main memory access is stored in the increment register 8 as an element interval, it can be processed in the same way as a vector operation instruction.

By performing operand address calculations as described above, MOVE instructions that read and write large amounts of data placed at consecutive addresses and vector operation instructions that handle large amounts of data placed at regular intervals can be processed extremely quickly. You will be able to do this. Furthermore, since the above-mentioned instructions are basically operated according to the instructions of the microprogram, complex instruction specifications can be realized without significantly increasing the amount of hardware. Furthermore, even if new instruction specifications are added in the future, this can be handled simply by changing the microprogram.

〔Effect of the invention〕

As described in detail above, according to the present invention, in an information processing device that performs instruction processing using pipeline control, it is possible to read and write data at high speed in consecutive addresses or addresses at regular intervals on the main memory. , This allows MOVE instructions, vector operation instructions, etc. to be processed at extremely high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an operand address calculation circuit within an instruction processing unit in a conventional information processing device, and FIG. 2 is a block diagram showing an embodiment of the present invention. 4... Adder (ADD), 5... Operand address register (AR), 6... Decoder (DEC), 7... Arithmetic unit (AU), 8... Increment register (ER),
21, 22, 23...Data selector.

Claims (1)

[Claims] 1. An instruction processing unit that decodes instructions, calculates operand addresses, reads operands, etc., a memory unit that stores operand data, and microinstructions stored in control memory for operands read from this memory unit. and a calculation unit that performs calculations under the instructions of
In a pipeline control type information processing device in which each of these units can operate in parallel, an operand address calculation circuit in the instruction processing unit selects an adder and information to be supplied to one input terminal of the adder. a first data selector that selects information to be supplied to the other input terminal of the adder; a first register that holds the addition result of the adder; and the adder, a third data selector for selecting the output of the adder or the information sent out from the arithmetic unit, and a third data selector provided between the second data selector and the arithmetic unit. and a circuit that supplies the output of the first register to one input terminal of the first data selector, and when the instruction processing unit is in a stopped state, The operand address calculation circuit controls the first, second, and third data selectors under the instruction of a microinstruction, and adds the contents of the first register and the second register. supply to the vessel,
An information processing device characterized in that an output of the adder can be stored in the first register.