KR102155479B1 - Semiconductor device - Google Patents

Abstract

A semiconductor device is provided. The semiconductor device sets a predetermined condition among a first layer image data for outputting a first frame image, a first memory in which the second layer image data is stored, and a plurality of unit elements for outputting a first frame image. By using a change map including information on the satisfied first unit element, location information on the first unit element is generated, and based on this, data on the first unit element among the first layer image data And a display controller that reads data on a first unit element among the second layer image data, and receives the generated location information and data on the read first unit element, and outputs a first frame image. It includes an interface for generating a command for updating a first unit element among a plurality of unit elements.

Description

Semiconductor device {Semiconductor device}

The present invention relates to a semiconductor device.

As the performance of electronic devices increases, the resolution of panels mounted on electronic devices is increasing day by day. Accordingly, power consumption of a driving system for driving a high-resolution panel is also increasing significantly.

The present invention is to provide a semiconductor device with reduced operating power consumption.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems that are not mentioned will be clearly understood by those skilled in the art from the following description.

In order to achieve the above technical problem, a semiconductor device according to an embodiment of the present invention includes a first layer image data for outputting a first frame image, a first memory storing second layer image data, and a first Using a change map including information on a first unit element that satisfies a predetermined condition among a plurality of unit elements for outputting a frame image, position information on the first unit element is generated, and A display controller that reads data for a first unit element among the first layer image data and reads data for a first unit element among the second layer image data, and the generated position information and the read first unit element And an interface for generating a command for updating a first unit element from among a plurality of unit elements for outputting a first frame image by receiving data for a first frame image.

In some embodiments of the present invention, the first layer image data is data used to display a partial region of the first frame image, and the second layer image data refers to another partial region of the first frame image. It may be data used to display.

In some embodiments of the present invention, the first memory further stores third layer image data used to display another partial area of the first frame image, and the display controller includes the third layer image data Among them, data on the first unit element may be further read.

In some embodiments of the present invention, the display controller and the interface may be disposed in an application processor (AP), and the first memory may be disposed outside the application processor.

In some embodiments of the present invention, the first unit element is a plurality of unit elements for outputting the first frame image when the image output to the output panel is changed from the second frame image to the first frame image It may be a unit element that needs to be changed.

In some embodiments of the present invention, the unit element may include a tile.

In some embodiments of the present invention, the second frame image may be output to the output panel before the first frame image.

In some embodiments of the present invention, the semiconductor device may further include a second memory in which the change map is stored.

In some embodiments of the present invention, the second memory, the display controller, and the interface may be disposed in an application processor (AP).

In some embodiments of the present invention, the display controller generates location information on the first unit element based on a change map decoder that decodes the change map and a decoding result of the change map decoder, and uses it in the interface. It may include a change map controller to provide.

In some embodiments of the present invention, the display controller includes: a first direct memory access (DMA) port for reading data on the first unit element among the first layer image data, and the second layer image data. A second DMA port for reading data on a first unit element, and a third DMA port different from the first and second DMA ports for providing the change map to the change map decoder.

In some embodiments of the present invention, the display controller reads information on the first layer image data from the change map and reads data on the first unit element from the first layer image data. A DMA port, and a second DMA port for reading information on the second layer image data of the change map and for reading data on the first unit element of the second layer image data.

In some embodiments of the present invention, the semiconductor device provides first and second layer image data for outputting a second frame image, and first and second layer image data for outputting the first frame image. It may further include a comparison unit that receives and generates the change map.

In some embodiments of the present invention, the comparison unit includes: a first generator configured to generate data for performing a cyclic redundancy check (CRC) for each unit element included in the first layer image data, and the second layer image And a second generator for generating data for performing CRC for each unit element included in the data, and a comparison logic for generating the change map by receiving the outputs of the first and second generators and performing the CRC. I can.

In some embodiments of the present invention, the interface may include HS/Link.

In order to solve the above technical problem, a semiconductor device according to another embodiment of the present invention includes first layer image data for outputting partial regions of first and second frame images, and other images of the first and second frame images. A first memory storing second layer image data for outputting a partial area; Comparing first layer image data for outputting a partial area of the first frame image and first layer image data for outputting a partial area of the second frame image, and outputting another partial area of the first frame image A first unit that needs to be changed among a plurality of unit elements for outputting the second frame image by comparing the second layer image data for outputting the second layer image data for outputting another partial area of the second frame image A comparison unit for generating a change map including information on elements; And reading data for the first unit element among first layer image data for outputting the second frame image, and among second layer image data for outputting the second frame image, using the change map. And a display controller that reads data on the first unit element.

In some embodiments of the present invention, the display controller includes: a first direct memory access (DMA) port for reading data on the first unit element from first layer image data for outputting the second frame image; A second DMA port for reading data on the first unit element from second layer image data for outputting the second frame image, and a third different from the first and second DMA ports receiving the change map May include a DMA port.

In some embodiments of the present invention, the display controller reads information on first layer image data for outputting the second frame image among the change maps, and the first unit element from the first layer image data A first DMA port that reads data for and information about second layer image data for outputting the second frame image from the change map, and from the second layer image data to the first unit element It may include a second DMA port to read the data.

In some embodiments of the present invention, the semiconductor device may further include a second memory in which the change map is stored.

In some embodiments of the present invention, the second memory and the display controller may be disposed in an application processor (AP).

According to another embodiment of the present invention for solving the above technical problem, a semiconductor device includes a frame buffer for buffering image data to be output to an output panel; When the image output on the output panel is changed from the first frame image to the second frame image, image data for a unit element that needs to be changed among a plurality of unit elements for outputting the second frame image is provided, and thus A frame buffer updater for updating image data stored in the corresponding frame buffer; And a driver for outputting an image signal based on image data stored in the frame buffer.

In some embodiments of the present invention, the image data includes first layer image data used to display a partial region of the second frame image, and a second layer used to display another partial region of the first frame image. May contain image data.

In some embodiments of the present invention, the unit element may include a tile.

In some embodiments of the present invention, the second frame image may be output later to the output panel than the first frame image.

Details of other embodiments are included in the detailed description and drawings.

1 is a block diagram of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a block diagram showing the configuration of the comparison unit of FIG. 1.
3 is a block diagram showing the configuration of the DDI (Display Driving Ic) of FIG. 1.
4 and 5 are flow charts illustrating an operation of a semiconductor device according to an exemplary embodiment of the present invention.
6 to 8 are diagrams for describing an operation of a semiconductor device according to an exemplary embodiment of the present invention.
9 is a block diagram of a semiconductor device according to another embodiment of the present invention.
10 is a block diagram of a semiconductor device according to another embodiment of the present invention.
11 is a block diagram of an SoC system employing a semiconductor device according to example embodiments.
12 is a block diagram illustrating a wireless communication device employing a semiconductor device according to embodiments of the present invention.
13 is a block diagram illustrating a configuration of an electronic system employing a semiconductor device according to example embodiments.
14 is a diagram illustrating an example in which the electronic system of FIG. 13 is applied to a smart phone.
15 is a diagram illustrating an example in which the electronic system of FIG. 13 is applied to a tablet PC.
16 is a diagram illustrating an example in which the electronic system of FIG. 13 is applied to a notebook computer.

Advantages and features of the present invention, and a method of achieving them will become apparent with reference to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms different from each other, and only these embodiments make the disclosure of the present invention complete, and common knowledge in the technical field to which the present invention pertains. It is provided to completely inform the scope of the invention to those who have it, and the invention is only defined by the scope of the claims. The sizes and relative sizes of components indicated in the drawings may be exaggerated for clarity of description. Throughout the specification, the same reference numerals refer to the same elements, and “and/or” includes each and all combinations of one or more of the recited items.

When one element is referred to as “connected to” or “coupled to” with another element, when directly connected or coupled to another element, or interposing another element in the middle Includes all cases. On the other hand, when one element is referred to as “directly connected to” or “directly coupled to” with another element, it indicates that no other element is intervened.

The terms used in the present specification are for describing exemplary embodiments and are not intended to limit the present invention. In this specification, the singular form also includes the plural form unless specifically stated in the phrase. As used in the specification, “comprises” and/or “comprising” do not exclude the presence or addition of one or more other elements other than the mentioned elements.

Although the first, second, etc. are used to describe various devices or components, it is a matter of course that these devices or components are not limited by these terms. These terms are only used to distinguish one device or component from another device or component. Therefore, it goes without saying that the first device or component mentioned below may be a second device or component within the technical idea of the present invention.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used as meanings that can be commonly understood by those of ordinary skill in the art to which the present invention belongs. In addition, terms defined in a commonly used dictionary are not interpreted ideally or excessively unless explicitly defined specifically.

Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 3.

1 is a block diagram of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of the comparison unit of FIG. 1. 3 is a block diagram showing the configuration of the DDI (Display Driving Ic) of FIG. 1.

Referring to FIG. 1, a semiconductor device 1 includes an application processor (AP) 10, a display driver IC (hereinafter referred to as DDI) 20, and a first memory 30 , And a second memory 40.

A plurality of layer image data L1 to Ln may be stored in the first memory 30.

In some embodiments of the present invention, the first memory 30 may include, for example, a volatile memory device. An example of such a volatile memory device may be a dynamic random access memory (DRAM), but the present invention is not limited thereto.

Meanwhile, in some other embodiments of the present invention, the first memory 30 may include, for example, a non-volatile memory device. Examples of such non-volatile memory devices include NAND flash, NOR flash, magnetic random access memory (MRAM), phase-change random access memory (PRAM), and resistive random access memory (RRAM). The invention is not limited thereto.

Meanwhile, in still other embodiments of the present invention, the first memory 30 may be modified and implemented as a hard disk drive or a magnetic memory device.

In the first memory 30, the plurality of layer image data L1 to Ln may be data used to output an image to an output panel. Specifically, each layer image data L1 to Ln may be data used to display a specific area of an image output on the output panel.

For example, if first to third layer image data (L1 to L3) is used to output an image to the output panel, the first layer image data (L1) is used to display the upper area of the image output to the output panel. The second layer image data (L2) is an image used to display the central area of the image output to the output panel, and the third layer image data (L3) represents the lower area of the image output to the output panel. It may be an image used to do.

Meanwhile, in some embodiments of the present invention, each of the plurality of layer image data L1 to Ln may include data used to output a plurality of frame images to an output panel.

For example, if first to third layer image data L1 to L3 are used to sequentially output a first frame image and a second frame image to the output panel, the first layer image data L1 is transferred to the output panel. An image used to display the upper regions of the first and second frame images output, and the second layer image data L2 is an image used to display the central regions of the first and second frame images output to the output panel And the third layer image data L3 may be an image used to display lower regions of the first and second frame images output to the output panel.

The plurality of layer image data L1 to Ln may be generated by an external image data generator and stored in the first memory 30. For example, the first layer image data L1 may be generated by a first application, the second layer image data L2 may be generated by a second application, and the third layer image data L3 May be generated by the third application, and the nth layer image data Ln may be generated by the nth application.

The AP 10 may receive a plurality of layer image data L1 to Ln from the first memory 30, process it, and provide the result to the DDI 20.

The AP 10 may include a comparison unit 12, a display controller 14, and an interface 18.

The term'unit' used in this embodiment refers to software or hardware components such as FPGA or ASIC, and the'unit' performs certain roles. However,'unit' is not meant to be limited to software or hardware. The'unit' may be configured to be in an addressable storage medium or may be configured to reproduce one or more processors. Thus, as an example, the'unit' refers to components such as software components, object-oriented software components, class components and task components, processes, functions, properties, procedures, Subroutines, segments of program code, drivers, firmware, microcode, circuitry, data, database, data structures, tables, arrays, and variables. The components and functions provided within the'units' may be combined into a smaller number of components and'units', or may be further divided into additional components and'units'.

Although, in FIG. 1, the comparison unit 12, the display controller 14, and the interface 18 are all included in the AP 10, the present invention is not limited thereto.

In some other embodiments of the present invention, the present embodiment may be modified so that some of these components are disposed outside the AP 10. For example, in some other embodiments of the present invention, the comparison unit 12 is disposed outside the AP 10, and the present embodiment is modified so that the display controller 14 and the interface 18 are disposed within the AP 10. Can be implemented.

The comparison unit 12 may generate a change map 42 by receiving a plurality of layer image data L1 to Ln stored in the first memory 30 and comparing them. The comparison unit 12 may store the generated change map 42 in the second memory 40.

1 and 2, the comparison unit 12 may include a plurality of generation units 12a-1 to 12a-n and a comparison logic 12b.

The plurality of generators 12a-1 to 12a-n receive a plurality of layer image data L1 to Ln, and receive a CRC for each unit element included in the plurality of layer image data L1 to Ln. Data for cyclic redundancy check) can be generated.

Specifically, the first generation unit 12a-1 generates data for performing CRC for each unit element included in the first layer image data L1 and provides the data to the comparison logic 12b, and the second generation unit (12a-2) generates data for performing CRC for each unit element included in the second layer image data L2 and provides it to the comparison logic 12b, and the third generation unit 12a-3 Data for performing CRC are generated for each unit element included in the three-layer image data L3 and provided to the comparison logic 12b, and the n-th generation units 12a-n are used for the n-th layer image data Ln. Data for performing CRC may be generated for each unit element included in the unit, and provided to the comparison logic 12b.

The comparison logic 12b may generate the change map 42 by receiving the outputs of the plurality of generators 12a-1 to 12a-n and performing CRC.

Specifically, the comparison logic 12b receives the output of the first generation unit 12a-1, performs CRC, and performs a change map 42 for the first layer image data L1 for outputting a specific frame image. Is generated, receives the output of the second generation unit 12a-2, performs CRC, generates a change map 42 for the second layer image data L2 for outputting a specific frame image, and a third Generates a change map 42 for the third layer image data L3 for outputting a specific frame image by receiving the output of the generation unit 12a-3 and performing CRC, and the n-th generation unit 12a-n A change map 42 for n-th layer image data Ln for outputting a specific frame image may be generated by performing CRC by receiving the output of ).

A more specific operation of the comparison unit 12 will be described later.

Referring to FIG. 1, in the present embodiment, a configuration in which the comparison unit 12 generates the change map 42 and stores the change map 42 in the second memory 40 is illustrated, but the present invention is not limited thereto. . For example, the change map 42 stored in the second memory 40 may be generated by an external component (eg, a graphical processing unit (GPU), a central processing unit (CPU)) not shown. . In other words, in some other embodiments of the present invention, the configuration of the comparison unit 12 may be omitted and implemented.

The second memory 40 that receives and stores the change map 42 from the comparison unit 12 may include, for example, a volatile memory device. An example of such a volatile memory device may be a dynamic random access memory (DRAM), but the present invention is not limited thereto.

Meanwhile, in some other embodiments of the present invention, the second memory 40 may include, for example, a non-volatile memory device. Examples of such non-volatile memory devices include static random access memory (SRAM), NAND flash, NOR flash, magnetic random access memory (MRAM), phase-change random access memory (PRAM), and resistive random access memory (RRAM). ) And the like, but the present invention is not limited thereto.

Meanwhile, in some other embodiments of the present invention, the second memory 40 may be modified to be a hard disk drive or a magnetic memory device.

Although the first memory 30 and the second memory 40 are separately illustrated in FIG. 1 for convenience of description, the present invention is not limited to the illustrated items. For example, in some embodiments of the present invention, the first memory 30 and the second memory 40 may be integrated into one implementation.

Also, in some other embodiments of the present invention, the first memory 30 and the second memory 40 may include different types of memories. For example, the first memory 30 may include DRAM, and the second memory 40 may include SRAM.

The display controller 14 uses the change map 42 to generate location information for some data that satisfies a predetermined condition for each of the plurality of layer image data L1 to Ln stored in the first memory 30, and , Based on this, some data of each of the plurality of layer image data L1 to Ln may be read.

In some embodiments of the present invention, some data satisfying such a predetermined condition may be some data that needs to be changed when, for example, an image output to the output panel is changed. A detailed description of this will also be described later.

The display controller 14 may include a change map decoder 15 and a change map controller 16.

The change map decoder 15 may receive the change map 42 and decode it, and the change map controller 16 may satisfy a predetermined condition described above based on the decoding result of the change map decoder 15. Position information for the data may be generated and provided to the interface 18.

Although FIG. 1 shows the change map decoder 15 and the change map controller 16 separately for convenience of description, the present invention is not limited thereto, and the change map decoder 15 and the change map controller 16 Any number of them can be integrated into one unit.

In this embodiment, when n layers of layer image data L1 to Ln are stored in the first memory 30, the display controller 14 includes n+1 Direct Memory Access (DMA) ports (DMA1 to DMA(n)). +1)) can be included. In other words, in the present embodiment, the number of DMA ports DMA1 to DMA(n+1) of the display controller 14 may be greater than the number of layer image data L1 to Ln stored in the first memory 30. .

For example, the first DMA port DMA1 is used to read some of the first layer image data L1 that satisfies the predetermined condition described above, and the second DMA port DMA2 is used to read the second layer image data. Among (L2), it is used to read some data that satisfies the predetermined condition described above, and the third DMA port (DMA3) reads some data of the third layer image data (L3) that satisfy the predetermined condition described above. The n-th DMA port DMAn is used to read some data of the n-th layer image data Ln that satisfies the predetermined condition described above, and the (n+1)-th DMA port (DMA(n+1) )) may be used to provide the change map 42 stored in the second memory 40 to the change map decoder 15.

However, the present invention is not limited to this example, and the allocation form of the DMA ports (DMA1 to DMA(n+1)) may be modified and implemented differently.

The interface 18 receives location information for some data that meets a predetermined condition from the change map controller 16, and sets a predetermined condition among a plurality of layer image data L1 to Ln from the display controller 14. Some data that satisfies may be provided, and a command to update them may be generated. In addition, the interface 18 may provide the received data 19 to the DDI 20 together with the generated command.

In some embodiments of the present invention, such interface 18 may include, for example, HS/Link, but the present invention is not limited thereto.

1 and 3, the DDI 20 may include a frame buffer updater 22, a frame buffer 24, a driver 26, and a timing controller 28.

The frame buffer 24 may be used to buffer image data. Accordingly, the frame buffer 24 may include a storage device for storing image data.

In some embodiments of the present invention, the frame buffer 24 may be implemented as a memory device, for example. In particular, in some embodiments of the present invention, the frame buffer 24 may be implemented as a static random access memory (SRAM). However, the present invention is not limited thereto, and the implementation form of the frame buffer 24 may be modified differently.

For example, in some other embodiments of the present invention, the frame buffer 24 is a different memory device (e.g., DRAM (Dynamic Random Access Memory), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory)). , PRAM (Phase Change Random Access Memory, etc.) may also be implemented.

The frame buffer updater 22 may update only the data 19 provided from the AP 10 among image data stored in the frame buffer 24. That is, the frame buffer updater 22 according to the present embodiment, of the image data used to display an image of one frame on the output panel stored in the frame buffer 24, only the data 19 provided from the AP 10 Can be updated.

The driver 26 may receive image data from the frame buffer 24, generate an image signal using the image data, and then provide it to the output panel. In some embodiments of the present invention, the image data provided from the frame buffer 24 may include, for example, digital data, and the image signal output from the driver 26 may include, for example, an analog signal. .

In some embodiments of the present invention, the driver 26 may include a gate driver and a source driver.

The gate driver may sequentially provide a gate driving signal to the output panel through the gate line in response to the control of the timing controller 28. Further, the source driver may provide an image signal to the output panel through the source line in response to the control of the timing controller 28 whenever gate lines are sequentially selected.

The output panel may include a plurality of pixels. In the output panel, a plurality of gate lines and source lines are arranged to cross each other in a matrix form, and such intersection points may be defined as pixels. In some embodiments of the present invention, each pixel may be composed of, for example, a plurality of dots (eg, RGB).

The timing controller 28 may control a source driver and a gate driver. The timing controller 28 may receive a plurality of control signals and data signals from an external system. The timing controller may generate a gate control signal and a source control signal in response to the received control signals and data signals, output the gate control signal to the gate driver, and output the source control signal to the source driver.

Hereinafter, an operation of a semiconductor device according to an exemplary embodiment will be described with reference to FIGS. 4 to 8.

4 and 5 are flow charts illustrating an operation of a semiconductor device according to an exemplary embodiment of the present invention. 6 to 8 are diagrams for describing an operation of a semiconductor device according to an exemplary embodiment of the present invention.

Hereinafter, as illustrated in FIG. 6, when outputting the n-th frame image Fn to the output panel, the first to third layer image data L1 to L3 are used, for example, in this embodiment. The operation of the semiconductor device according to will be described. However, this is only an example, and the present invention is not limited to this example.

First, referring to FIG. 6, when the n-th frame image Fn is output to the output panel, the first layer image data L1 is used to output the upper 2 columns of the n-th frame image Fn. The second layer image data L2 is used to output the next 4 columns of the n-th frame image Fn, and the third layer image data L3 is used to output the next 1 column of the n-th frame image Fn. Can be used.

Each of the first to third layer image data L1 to L3 may include a plurality of unit elements UE. In the present embodiment, the unit element UE may be, for example, a tile, but the present invention is not limited thereto.

As illustrated, the first layer image data L1 may be divided into 10 unit elements UE, and the second layer image data L2 may be divided into 20 unit elements UE. The three-layer image data L3 may be divided into five unit elements UE.

The operation of the semiconductor device according to the present embodiment, which will be described below, assumes that the n-th frame image Fn shown in FIG. 6 has already been displayed on the output panel, and is now displayed on the output panel. 1) The description will focus on the process of outputting the frame image (F(n+1)).

4, a change map is generated (S100).

Specifically, referring to FIG. 5, first, data for performing CRC is generated for each unit element UE included in the first to third layer image data L1 to L3 (S110).

2, the first generation unit 12a-1 of the comparison unit 12 receives the first layer image data L1 stored in the first storage unit 30, and receives the first layer image data L1. Data for performing CRC may be generated for each unit element (UE) included in the UE.

In addition, the second generation unit 12a-2 of the comparison unit 12 receives the second layer image data L2 stored in the first storage unit 30, and receives each of the second layer image data L2. Data for performing CRC can be generated for each unit element (UE).

In addition, the third generation unit 12a-3 of the comparison unit 12 receives the third layer image data L3 stored in the first storage unit 30, and receives each of the third layer image data L3. Data for performing CRC can be generated for each unit element (UE).

Next, referring again to FIG. 5, CRC is performed (S120).

Referring to FIG. 2, the comparison logic 12b of the comparison unit 12 receives the output of the first generation unit 12a-1 and performs CRC to determine a predetermined condition among the first layer image data L1. The unit element (UE) that satisfies can be selected.

For example, when the image output to the output panel is changed from the nth frame image Fn shown in FIG. 6 to the (n+1)th frame image F(n+1) shown in FIG. Two unit elements UE of the first layer image data L1 need to be changed. Accordingly, the comparison logic 12b may select these two unit elements UE from among the first layer image data L1.

In addition, the comparison logic 12b of the comparison unit 12 receives the output of the second generation unit 12a-2 and performs CRC, so that a unit element that satisfies a predetermined condition among the second layer image data L2 (UE) can be selected.

For example, when the image output to the output panel is changed from the nth frame image Fn shown in FIG. 6 to the (n+1)th frame image F(n+1) shown in FIG. It is necessary to change three unit elements UE of the second layer image data L2. Accordingly, the comparison logic 12b may select these three unit elements UE from among the second layer image data L2.

In addition, the comparison logic 12b of the comparison unit 12 receives the output of the third generation unit 12a-3 and performs CRC, so that a unit element that satisfies a predetermined condition among the third layer image data L3 (UE) can be selected.

For example, when the image output to the output panel is changed from the nth frame image Fn shown in FIG. 6 to the (n+1)th frame image F(n+1) shown in FIG. In the third layer image data L3, there is no need to change the unit element UE. Accordingly, the comparison logic 12b may not select the unit element UE from among the third layer image data L2.

When the operation of selecting a unit element UE that satisfies a predetermined condition among the first to third layer image data L1 to L3 is completed, the comparison logic 12b generates a change map as shown in FIG. Thus, it can be stored in the second storage unit 40.

In FIG. 8, when the image output to the output panel is changed from the nth frame image Fn shown in FIG. 6 to the (n+1)th frame image F(n+1) shown in FIG. This required unit element (UE) is indicated by hatching.

Although described above, the change map 42 stored in the second storage unit 40 may also be generated by components other than the comparison unit 12. That is, the present invention is not limited to this example.

Next, referring again to FIG. 4, the change map is decoded (S200).

Specifically, referring to FIG. 1, the change map decoder 15 receives the change map 42 from the second memory 40 through the (n+1)th DMA port (DMA(n+1)), It can be decoded.

Subsequently, the change map controller 16 receives the decoding result for the change map 42 from the change map decoder 15, and the image output to the output panel is shown in the n-th frame image Fn shown in FIG. When it is changed to the (n+1)th frame image F(n+1) shown in FIG. 7, position information on the unit element UE that needs to be changed may be generated.

Next, referring to FIG. 4 again, image data is read (S300).

Specifically, referring to FIG. 1, the display controller 14 displays an image output to the output panel among the first to third layer image data L1 to L3 stored in the first memory 30. When the n-frame image Fn is changed to the (n+1)th frame image F(n+1) shown in FIG. 7, data on the unit element UE that needs to be changed may be read.

Specifically, the display controller 14 displays an image output to the output panel among the first layer image data L1 through the first DMA port DMA1 in the n-th frame image Fn shown in FIG. 6. When the image is changed to the (n+1)th frame image F(n+1) shown in FIG. 7, data for two unit elements UE that needs to be changed may be read.

That is, the display controller 14 does not read all the first layer image data L1 used to output the (n+1)th frame image F(n+1) shown in FIG. 7, When the image output to the output panel is changed from the n-th frame image Fn shown in FIG. 6 to the (n+1)th frame image F(n+1) shown in FIG. Only data for two unit elements (UE) can be read.

In addition, the display controller 14 transmits the image output to the output panel among the second layer image data L2 through the second DMA port DMA2 from the n-th frame image Fn shown in FIG. 6 to FIG. 7. When the image is changed to the (n+1)th frame image F(n+1) shown in, data for three unit elements UE that needs to be changed may be read.

That is, the display controller 14 does not read all the second layer image data L2 used to output the (n+1)th frame image F(n+1) shown in FIG. 7, When the image output to the output panel is changed from the nth frame image Fn shown in FIG. 6 to the (n+1)th frame image F(n+1) shown in FIG. Only data for two unit elements (UE) can be read.

Meanwhile, in the third layer image data L3, the image output to the output panel is the (n+1)th frame image F(n+) shown in FIG. 7 from the nth frame image Fn shown in FIG. When changed to 1)), since the changed unit element UE does not exist, the display controller 14 may not perform a read operation through the third DMA port DMA3.

Thereafter, the image generated by the change map controller 16 and output to the output panel is from the nth frame image Fn shown in FIG. 6 to the (n+1)th frame image F(n+) shown in FIG. When changed to 1)), location information on the unit element UE that needs to be changed may be provided to the interface 18.

In addition, some data that needs to be changed among the first to third layer image data L1 to L3 read by the display controller 14 may be provided to the interface 18.

The interface 18 may generate a command for updating the provided data 19 and the provided data 19 and provide them to the DDI 20.

Next, referring again to FIG. 4, the frame buffer is updated (S400).

Specifically, referring to FIG. 3, the frame buffer updater 22 may update only the received data 19 among image data stored in the frame buffer 24. Since the provided data 19 also includes location information of data that needs to be updated, this operation can be easily performed.

When the image data stored in the frame buffer 24 is updated in this way, and then an image is displayed on the output panel using this, the (n+1)th frame image F(n+1) shown in FIG. 7 is displayed on the output panel. ) May be displayed.

As described above, in the semiconductor device 1 according to the present exemplary embodiment, when the image displayed on the display panel is changed, only data that satisfies a predetermined condition among the plurality of layer image data L1 to Ln is read. Accordingly, power consumption for a data read operation can be reduced.

In addition, in the semiconductor device 1 according to the present embodiment, when an image displayed on the display panel is changed, only data that satisfies a predetermined condition among image data stored in the frame buffer 24 is updated. Accordingly, the driving power of the DDI 20 can be reduced.

Hereinafter, referring to FIG. 9, a semiconductor device according to another embodiment of the present invention will be described.

9 is a block diagram of a semiconductor device according to another embodiment of the present invention. Hereinafter, differences from the above-described embodiments will be mainly described.

Referring to FIG. 9, the number of display controllers 14a included in the AP 10a of the semiconductor device 2 is smaller than that of the display controller (14 of FIG. 1) of the semiconductor device (1 of FIG. 1) described above. DMA ports (DMA1 ~ DMAn) may be included.

Specifically, in the display controller (14 of FIG. 1) of the semiconductor device (1 of FIG. 1) described above, a separate DMA port for receiving the change map 42 (for example, DMA (n+1) of FIG. 1) ), but in the present embodiment, such a separate DMA port may be omitted.

In this embodiment, when n layers of layer image data (L1 to Ln) are stored in the first memory 30, the display controller 14 may include n direct memory access (DMA) ports (DMA1 to DMAn). I can. In other words, in the present embodiment, the number of DMA ports DMA1 to DMAn of the display controller 14a may be the same as the number of layer image data L1 to Ln stored in the first memory 30.

In the semiconductor device 2 according to the present embodiment, the display controller 14a reads the change map 42 in the form of, for example, a packet header through each of the plurality of DMA ports DMA1 to DMAn. This can be provided to the change map decoder 15a and the change map controller 16a.

And, the display controller 14a, based on the outputs of the change map decoder 15a and the change map controller 16a, selects some of the plurality of layer image data L1 to Ln that satisfy the predetermined condition described above. I can lead.

For example, the first DMA port DMA1 reads information on the first layer image data L1 in the change map 42, and satisfies the predetermined condition described above among the first layer image data L1. It can be used to read some data.

The second DMA port DMA2 reads information on the second layer image data L2 from the change map 42, and reads some data from the second layer image data L2 that satisfy the predetermined conditions described above. Can be used to

The third DMA port DMA3 reads information on the third layer image data L3 from the change map 42, and reads some data from the third layer image data L3 that satisfy the predetermined conditions described above. Can be used to

The n-th DMA port (DMAn) reads information on the n-th layer image data Ln of the change map 42, and reads some data of the n-th layer image data Ln that satisfy the predetermined condition described above. Can be used to

Next, a semiconductor device according to another embodiment of the present invention will be described with reference to FIG. 10.

10 is a block diagram of a semiconductor device according to another embodiment of the present invention. Hereinafter, differences from the above-described embodiments will be mainly described.

Referring to FIG. 10, the AP 10c of the semiconductor device 3 according to the present embodiment may include a second memory 40 in which a change map 42 is stored. In other words, in the semiconductor device 3 according to the present embodiment, the second memory 40 for storing the change map 42 may be disposed in the AP 10c.

In some embodiments of the present invention, the second memory 40 may be implemented as, for example, SRAM, but the present invention is not limited thereto.

11 is a block diagram of an SoC system employing a semiconductor device according to example embodiments.

Referring to FIG. 11, the SoC system 800 may include an application processor 801, a DRAM 860, and a DDI 890.

The application processor 801 may include a central processing unit 810, a multimedia system 820, a bus 830, a memory system 840, and a peripheral circuit 850.

The central processing unit 810 may perform an operation required to drive the SoC system 800. In some embodiments of the present invention, the central processing unit 810 may be configured in a multi-core environment including a plurality of cores.

The multimedia system 820 may be used to perform various multimedia functions in the SoC system 800. The multimedia system 820 may include a 3D engine module, a video codec, a display system, a camera system, a post-processor, and the like. .

In some embodiments of the present invention, the multimedia system 820 may include the display controllers 14 and 14a of the semiconductor devices 1 to 3 according to the exemplary embodiments described above.

The bus 830 may be used for the central processing unit 810, the multimedia system 820, the memory system 840, and the peripheral circuit 850 to communicate data with each other. In some embodiments of the present invention, such a bus 830 may have a multilayer structure. Specifically, as an example of the bus 830, a multi-layer Advanced High-performance Bus (AHB) or a multi-layer Advanced eXtensible Interface (AXI) may be used, but the present invention is not limited thereto.

The memory system 840 may provide an environment required for high-speed operation by connecting the application processor 801 to an external memory (eg, the DRAM 860). In some embodiments of the present invention, the memory system 840 may include a separate controller (eg, a DRAM controller) for controlling an external memory (eg, the DRAM 860).

The peripheral circuit 850 may provide an environment necessary for the SoC system 800 to be smoothly connected to an external device (eg, a main board). Accordingly, the peripheral circuit 850 may have various interfaces that allow external devices connected to the SoC system 800 to be compatible.

The DRAM 860 may function as an operating memory required for the application processor 801 to operate. In some embodiments of the present invention, the DRAM 860 may be disposed outside the application processor 801 as shown. Specifically, the DRAM 860 may be packaged in the form of an application processor 801 and a PoP (Package on Package).

In some embodiments of the present invention, the DRAM 860 may store the first to nth layer image data L1 to Ln of the semiconductor devices 1 to 3 according to the exemplary embodiments described above.

12 is a block diagram illustrating a wireless communication device employing a semiconductor device according to embodiments of the present invention.

Referring to FIG. 12, the device 900 may be a cellular telephone, a smart phone terminal, a handset, a personal digital assistant (PDA), a laptop computer, a video game unit, or other device. The device 900 may use code division multiple access (CDMA), time division multiple access (TDMA) such as Global System for Mobile Communications (GSM), or other wireless communication standards.

Device 900 may provide two-way communication via a receive path and a transmit path. Signals transmitted by one or more base stations on the reception path may be received by the antenna 911 or may be provided to the receiver RCVR 913. The receiver 913 may condition and digitize the received signal and provide samples to the digital section 920 for further processing. On the transmission path, the transmitter (TMTR, 915) receives the transmitted data from the digital section 920, processes and conditions the data, and generates a modulated signal, the modulated signal through the antenna 911. It may be transmitted to one or more base stations.

The digital section 920 may be implemented with one or more digital signal processors (DSPs), micro-processors, reduced instruction set computers (RISCs), and the like. Further, the digital section 920 may be fabricated on one or more application specific integrated circuits (ASICs) or other types of integrated circuits (ICs).

The digital section 920 is, for example, a modem processor 934, a video processor 922, an application processor 924, a display processor 928, a multicore processor 926, a central processing unit 930, and It may include various processing and interface units such as external bus interface 932.

Modem processor 934, video processor 922, application processor 924, display processor 928, multicore processor 926, central processing unit 930, and external bus interface 932 as shown. They can be connected to each other via a bus.

The video processor 922 may perform processing for graphics applications. In general, video processor 922 may include any number of processing units or modules for any set of graphics operations.

Certain portions of video processor 922 may be implemented in firmware and/or software. For example, the control unit may be implemented with firmware and/or software modules (eg, procedures, functions, etc.) that perform the functions described above. Firmware and/or software codes may be stored in memory and executed by a processor (eg, multi-core processor 926). The memory may be implemented in the processor or may be implemented outside the processor.

The video processor 922 may implement a software interface such as an open graphic library (OpenGL) or Direct3D.

The central processing unit 930 may perform a series of graphic processing operations together with the video processor 922.

In some embodiments of the present invention, the change map 42 of the semiconductor devices 1 to 3 according to the embodiments of the present invention described above is generated by at least one of the video processor 922 or the central processing unit 930. I can.

The multi-core processor 926 may include at least two cores and allocate a workload to two cores according to a workload to be processed by the multi-core processor 926 to simultaneously process the corresponding workload.

The display processor 928 may perform various processing on an image output to the display 910.

At least one of the application processor 924 and the display processor 928 may employ the configurations of the semiconductor devices 1 to 3 according to the exemplary embodiments described above.

The modem processor 934 may perform various processing related to communication within the digital section 920.

The external bus interface 932 may be connected to the external mevory 940.

13 is a block diagram illustrating a configuration of an electronic system employing a semiconductor device according to example embodiments.

Referring to FIG. 13, the electronic system 1000 may include a memory system 1002, a processor 1004, a RAM 1006, a user interface 1008, and a DDI 1010.

The memory system 1002, the processor 1004, the RAM 1006, the user interface 1008, and the DDI 1010 may communicate with each other using a bus 1010.

The processor 1004 may play a role of executing a program and controlling the electronic system 1000, among at least one microprocessor, a digital signal processor, a microcontroller, and logic elements capable of performing functions similar to these. It may include at least any one.

The RAM 1006 may be used as an operating memory of the processor 1004. The RAM 1006 may be formed of, for example, a volatile memory such as DRAM. Meanwhile, the processor 1004 and the RAM 1006 may be packaged and implemented as a single semiconductor device or a semiconductor package.

The user interface 1008 may be used to input or output data to the electronic system 1000. Examples of the user interface 1008 include a keypad, a keyboard, an image sensor, and a display device.

The memory system 1002 may store codes for operation of the processor 1004, data processed by the processor 1004, or data input from an external device. The memory system 1002 may include a separate controller for driving, and may be configured to additionally include an error correction block. The error correction block may be configured to detect and correct an error in data stored in the memory system 1002 using an error correction code (ECC).

Meanwhile, in an information processing system such as a mobile device or a desktop computer, a flash memory may be mounted as the memory system 1002. Such a flash memory may be configured as a semiconductor disk device (SSD; Solid State Drive). In this case, the electronic system 1000 may stably store a large amount of data in the flash memory.

The memory system 1002 may be integrated into one semiconductor device. For example, the memory system 1002 may be integrated into one semiconductor device to form a memory card. For example, the memory system 1002 is integrated into a single semiconductor device and is a PC card (PCMCIA, personal computer memory card international association), a compact flash card (CF), a smart media card (SM, SMC), a memory stick, and a multimedia device. Memory cards such as cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), and universal flash memory devices (UFS) can be configured.

In some embodiments of the present invention, the DDI 1010 may employ the configuration of the DDI 20 of the semiconductor devices 1 to 3 according to the exemplary embodiments described above.

The electronic system 1000 illustrated in FIG. 13 may be applied to an electronic control device of various electronic devices. 14 is a diagram illustrating an example in which the electronic system of FIG. 13 is applied to a smart phone.

As described above, when the electronic system (1000 in FIG. 13) is applied to the smart phone 1001, some components of the electronic system (1000 in FIG. 13) may be implemented as an application processor.

Meanwhile, the electronic system (1000 in FIG. 13) may be employed in other electronic devices. 15 is a diagram illustrating an example in which the electronic system 1000 of FIG. 13 is applied to the tablet PC 1100, and FIG. 16 is a diagram illustrating an example in which the electronic system 1000 of FIG. 13 is applied to the notebook 1200 It is a drawing.

In addition, the electronic system (1000 in Fig. 13) is a personal computer, UMPC (Ultra Mobile PC), workstation, net-book, PDA (Personal Digital Assistants), portable computer, web tablet. ), wireless phone, mobile phone, e-book, portable multimedia player (PMP), portable game console, navigation device, black box, digital camera (digital camera), 3-dimensional television, digital audio recorder, digital audio player, digital picture recorder, digital picture player , A digital video recorder, a digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, various electronic devices constituting a computer network One of the various electronic devices constituting a telematics network, an RFID device, or one of various elements constituting a computing system may be provided as one of various elements of an electronic device.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to the above embodiments, but may be manufactured in various different forms, and those skilled in the art to which the present invention pertains. It will be understood that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not limiting.

10: AP
20: DDI
30, 40: memory

Claims (20)

A first memory in which first layer image data for outputting a first frame image and second layer image data are stored;
Using a change map including information on a first unit element that satisfies a predetermined condition among a plurality of unit elements for outputting the first frame image, location information on the first unit element is A display controller configured to generate and read data for the first unit element among the first layer image data and read data for the first unit element among the second layer image data based on the generated data; And
And an interface for generating a command for updating the first unit element among a plurality of unit elements for outputting the first frame image by receiving the generated location information and data on the read first unit element But,
The first unit element is a unit element that needs to be changed from the second frame image among a plurality of unit elements for outputting the first frame image when it is changed from the second frame image to the first frame image,
The location information on the first unit element is location information on the first unit element that needs to be changed from the second frame image in order to output the first frame image. The method of claim 1,
The first layer image data is data used to display a partial area of the first frame image,
The second layer image data is data used to display another partial area of the first frame image. The method of claim 2,
The first memory further stores third layer image data used to display another partial area of the first frame image,
The display controller further reads data on the first unit element among the third layer image data. The method of claim 1,
The display controller and the interface are disposed in an application processor (AP),
The first memory is a semiconductor device disposed outside the application processor. delete The method of claim 1,
The unit element is a semiconductor device including a tile. The method of claim 1,
The second frame image is output to the output panel before the first frame image. The method of claim 1,
The semiconductor device further comprising a second memory in which the change map is stored. The method of claim 8,
The second memory, the display controller, and the interface are disposed in an application processor (AP). The method of claim 1,
The display controller,
A change map decoder that decodes the change map,
And a change map controller that generates location information on the first unit element based on a result of decoding by the change map decoder and provides it to the interface. The method of claim 10,
The display controller,
A first direct memory access (DMA) port for reading data on the first unit element among the first layer image data;
A second DMA port for reading data on the first unit element among the second layer image data,
And a third DMA port different from the first and second DMA ports for providing the change map to the change map decoder. The method of claim 10,
The display controller,
A first DMA port for reading information on the first layer image data in the change map and for reading data on the first unit element in the first layer image data,
And a second DMA port for reading information on the second layer image data in the change map and for reading data on the first unit element in the second layer image data. The method of claim 1,
Further comprising: a comparison unit receiving first and second layer image data for outputting a second frame image and first and second layer image data for outputting the first frame image and generating the change map Semiconductor device. The method of claim 13,
The comparison unit,
A first generator for generating data for performing a cyclic redundancy check (CRC) for each unit element included in the first layer image data;
A second generator for generating data for performing CRC for each unit element included in the second layer image data,
And a comparison logic configured to generate the change map by receiving the outputs of the first and second generation units and performing the CRC. The method of claim 1,
The interface is a semiconductor device including HS/Link. A first memory in which first layer image data for outputting partial regions of the first and second frame images and second layer image data for outputting other partial regions of the first and second frame images;
Comparing first layer image data for outputting a partial area of the first frame image and first layer image data for outputting a partial area of the second frame image, and outputting another partial area of the first frame image A first unit that needs to be changed among a plurality of unit elements for outputting the second frame image by comparing the second layer image data for outputting the second layer image data for outputting another partial area of the second frame image A comparison unit for generating a change map including information on elements; And
By using the change map, data for the first unit element is read among first layer image data for outputting the second frame image, and the second layer image data for outputting the second frame image. A semiconductor device including a display controller that reads data on a first unit element. The method of claim 16,
The display controller,
A first direct memory access (DMA) port for reading data on the first unit element from first layer image data for outputting the second frame image;
A second DMA port for reading data on the first unit element from second layer image data for outputting the second frame image;
A semiconductor device comprising a third DMA port different from the first and second DMA ports to be provided with the change map. The method of claim 16,
The display controller,
A first DMA port for reading information on first layer image data for outputting the second frame image from the change map, and for reading data on the first unit element from the first layer image data;
A second DMA port for reading information on second layer image data for outputting the second frame image from the change map, and for reading data on the first unit element from the second layer image data Semiconductor device. A frame buffer for buffering image data to be output to the output panel;
When the image output on the output panel is changed from the first frame image to the second frame image, image data for a unit element that needs to be changed among a plurality of unit elements for outputting the second frame image is provided, and thus A frame buffer updater for updating image data stored in the corresponding frame buffer; And
And a driver for outputting an image signal based on image data stored in the frame buffer. The method of claim 19,
The image data includes first layer image data used to display a partial region of the second frame image and second layer image data used to display another partial region of the first frame image.

Images