CN1766860A - Interrupt control handling apparatus and method - Google Patents
Interrupt control handling apparatus and method Download PDFInfo
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Abstract
The invention discloses a break control processor which comprises a break generating unit used to generate the breaking, a break mark register used to register the break generated by the break generating unit and combines to form a break application, a break control unit used to sieve the break application and choose the best break application to the break processing unit to process it, a break processing unit used to receive the break application sieved by the break control unit and process it. It also discloses a break control method.
Description
Technical field
The present invention relates to the circuit system design field, relate in particular to a kind of interrupt control treating apparatus and method.
Background technology
In the circuit system design, the processor in the circuit system is when carrying out processing instruction, and central processing unit can asynchronous or synchronous event interruptions by some continually.
Above-mentioned asynchronous or synchronous event is called as and interrupts or unusual.
Interruption is an asynchronous event, mainly by hardware, as I/O (I/O) equipment, processor call, clock or timer cause, is the incident of the interrupt processor that takes place at random; Unusually being synchronous event, is the result that some specific instruction is carried out, and zero is removed, calculates and overflow etc. as main memory access mistake, floating number.Generally, anomaly ratio interrupts much frequent.
As shown in Figure 1, the Interrupt Process device that is used for Circuits System in the prior art comprises that one interrupts producing part 11, is used for producing interrupting, and forms and interrupts application, comprise and interrupt 0 ..., interrupt n; An interrupt control part 12 is used for therefrom suitable interruption application of stopping pregnancy first portion 11 selection outputs; And an Interrupt Process part 13, be used for the interruption application of selecting on the handling interrupt control section 12.Interrupting application can be the level formula, also can be pulsed.
Along with the product systems design becomes increasingly complex, the number and the frequency of interruption increase significantly.These interruptions are necessary, because they support the processing of the execution of a plurality of processing procedures, a plurality of peripheral hardwares and the performance monitoring of each assembly.But simultaneously, during each Circuits System design the getable pin that awards interruption but be limited, contradiction has just produced.
In addition, ideally, after interrupting applying for producing, disposal system can be handled according to above-mentioned steps, carries out normal interrupt handling routine then.Yet software systems need certain hour for the processing of interrupting, and still have new interruption and take place in this time period, propose new interruption application to interrupt processing system; So, when the Interrupt Process part may not have time enough to handle an interruption, the next interruption just arrived, and just have to abandon this application owing to can not get response; For the pulse-break application, several clock period are only arranged, if send when interrupting application, disposal system is busy, and disposal system is easy to neglect this interruption application so, and in this case, disposal system tends to lose important interruption.If be left in the basket or the interruption that abandons be the interruption that must handle in the circuit system, will cause system to make mistakes.
Moreover for the look-at-me of all generations, interrupt control part 12 often needs to control carefully and could guarantee that all interruptions all obtain handling, otherwise, be left in the basket or the interruption that abandons will cause system mistake.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of interrupt control treating apparatus, when solving the underway disconnected processing of prior art, interrupt pin is too much, makes troubles to design;
Another purpose of the present invention is, a kind of interrupt control treating apparatus is provided, and interval between the application is too short to make interrupt handler have little time to carry out interrupt response and cause the problem of interrupting losing solve to interrupt;
Another purpose of the present invention is, a kind of interrupt control treating apparatus is provided, and causes interrupting applying for sending the problem of not lost by response to solve the Interrupt Process overlong time;
A further object of the present invention is, a kind of interrupt control disposal route is provided, to improve the Interrupt Process process effectively.
For addressing the above problem, the invention provides following technical scheme:
A kind of Interrupt Process device is characterized in that comprising:
Interrupt generating unit comprises one or more interrupt sources, is used for producing interrupting;
Interrupt flag register is used to deposit the interruption that described interrupt generating unit is sent, and forms interrupt identification;
The interrupt control unit is used for above-mentioned interrupt identification is made up, and generates to interrupt applying for giving the Interrupt Process unit, handles;
The Interrupt Process unit is used to accept the interruption application of described interrupt control unit generation and handle.
Further, also include a delay unit in the interrupt control unit, be used for the interruption application that receives is reasonably postponed, give enough processing times of described Interrupt Process unit, guarantee that interruption application afterwards is not dropped;
Further, the delay time of described delay unit can use software to be provided with according to system's needs at interval;
Further, described delay time can be set to 0 at interval;
Further, described delay unit can be set to use or do not use;
Further, also comprise a regularly retransmission unit in the described interrupt control unit, be used for, make this interruption application constantly be sent to described Interrupt Process unit not retransmitted by the interruption application of described Interrupt Process cell response;
Further, the timing repetition cycle of described timing retransmission unit can use software to be provided with as required
Further, also disposed the FIFO buffer before described interrupt generating unit and interrupt flag register, preserving does not have processed interruption;
Further, described interrupt source is original interrupt source or non-original interrupt source, be implemented as follows: form different elementary interrupt generating unit after being divided into groups in a plurality of original interrupt source, described elementary interrupt generating unit can be assigned with uses an elementary interrupt flag register; Then with above-mentioned elementary interrupt flag register as new " interrupt source ", non-original interrupt source forms described interrupt generating unit; By this processing, interruption that can a plurality of interrupt sources are required lead-in wire reduces to that Circuits System allows;
Further, when the interrupt generating unit of interrupt control treating apparatus is divided into groups to the original interrupt source, can be according to the importance of interrupt source, occurrence frequency and this interrupt routine take the Interrupt Process unit time and take all factors into consideration the grouping situation, to reach the evenly purpose of the interrupt source of each group.
A kind of interrupt control disposal route may further comprise the steps:
A produces interruption;
The interruption that B will produce deposits in the interrupt flag register, forms interrupt identification;
C utilizes the interrupt control unit, all interrupt identification combinations is generated interrupt applying for offering the Interrupt Process unit;
This interruption application is accepted in D Interrupt Process unit, enters the program of handling interrupt, and next step that finish that this interruptions applies for by the Interrupt Process unit judges whether to carry out this interrupt handling routine.
Further, among the described step C, before giving the Interrupt Process unit, can make certain delay process to this interruption application with interruption;
Further, whether described delay process can be selected to carry out;
Further, step C executes, and when interrupting not by described Interrupt Process cell response, this is interrupted application make regularly retransmission process, should interrupt application up to the Interrupt Process cell processing.
The contrast prior art, the present invention has well solved the few contradiction of disrupted circuit pin that number of interruptions is many and Circuits System is provided, simultaneously, efficiently solving interruption by increase time-delay and timing retransmitting function frequently takes place and the slow contradiction of interrupt handling routine processing speed, the interruption application of having sent when having avoided owing to system busy is left in the basket, and the situation of losing of the interruption application that causes takes place.
Description of drawings
Fig. 1 handles synoptic diagram for prior art interrupt control commonly used;
Fig. 2 is an interrupt control treating apparatus synoptic diagram of the present invention;
Fig. 3 is the interrupt control treating apparatus synoptic diagram that delay unit is arranged;
Fig. 4 is the selectable interrupt control treating apparatus of a delay unit synoptic diagram;
Fig. 5 has the regularly interrupt control treating apparatus synoptic diagram of retransmission unit;
Fig. 6 is the Interrupt Process device synoptic diagram that delay unit and timing retransmission unit are arranged;
Fig. 7 carries out the synoptic diagram of multiple-stage treatment for interrupt source;
Fig. 8 has the interruption processing method process flow diagram of time-delay and timing retransmitting function.
Embodiment
As shown in Figure 2, interrupting generating unit 21 links to each other with interrupt flag register 24, the information in the interrupt flag register 24 is read in interruption application 120 in the interrupt control unit 12, by the control of interrupt control unit 12, send application to Interrupt Process unit 23, require to interrupt, after Interrupt Process unit 23 receives application, enter the program of handling interrupt, under the situation of conditions permit, just enter the interrupt handling routine of corresponding interruption.After interrupt handling routine executed, just the position with the corresponding interrupt source in the corresponding interrupt flag register resetted.
Each is interrupted all being deposited with in each position of interrupt register, form interrupt identification, and for each interrupt source disposes an enable bit, like this enabling or forbid it all being mutually non-interfering each interruption.Interrupt source 210 and interrupt flag register 24 link, and a corresponding interrupt source 210 is arranged in the interrupt register 24, and interrupt source 210 is had no progeny in taking place, and under the control of the interrupt enable bit of interrupt source 210, fill in corresponding position in the interrupt flag register 24.After interruption application 120 perceives the information of interrupting taking place, just read the information of interrupt flag register 24, control by interrupt control unit 12, send application to Interrupt Process unit 23, illustrate that interrupt source 210 has interruption, the Interrupt Process unit draws the decision whether interrupt in handling interrupt source 210 according to the comparison principle of oneself.
As shown in Figure 3, apply for that in the interruption of interrupt control unit 12 120 back increase a delay unit 121, when above-mentioned processing, after an interruption application is sent by interruption application 120,, send to Interrupt Process unit 23 again through after the time-delay of delay unit 121; For example interrupt source 210 has been interrupted, behind said process, Interrupt Process unit 23 is in the interruption in handling interrupt source 210, this moment, interrupt source 211 has been interrupted again, if there is not delay unit 121, two times of interrupting taking place are very approaching, the interrupt handling routine of interrupt source 210 is not also finished, and Interrupt Process unit 23 can not be accepted to interrupt 211 interruption application, so the interruption application of interrupt source 211 has just been lost; Because delay unit 121 has been arranged,, come the interrupt routine in handling interrupt source 210 for Interrupt Process unit 23 time enough so the interruption application of interrupt source 211 is delayed time after a while at delay unit 121 back warps and sent out.When sending application once more, just can be interrupted processing unit 23 and accept.The delay time of delay unit 121 can be controlled according to the demand of system by software at interval.
Shown in Figure 4 is when containing delay unit 121 in interrupt control unit 12, can after interrupting application 120, connect a selector switch 123, the input end of delay unit 121 applies for that with interrupting 120 link to each other, output terminal links to each other with selector switch 123, selector switch 123 input ends apply for that with interrupting 120 link to each other with delay unit 121, and output terminal links to each other with Interrupt Process unit 23.Can reach the purpose that whether needs to carry out delay process by control selector switch 123.
As shown in Figure 5, apply for that in the interruption of interrupt control unit 12 120 back increase a regularly retransmission unit 124, during underway disconnected processings, one interrupt application by interrupt applying for 120 send after, through the regularly timing of retransmission unit 124, resend to Interrupt Process unit 23; For example interrupt source 210 has been interrupted, behind said process, Interrupt Process unit 23 is in the interruption in handling interrupt source 210, this moment, interrupt source 211 has been interrupted again, if there is not regularly retransmission unit 121, it is chronic that 210 interrupt sources take Interrupt Process unit 23, the interrupt handling routine of interrupt source 210 is not also finished, and Interrupt Process unit 23 can not be accepted to interrupt 211 interruption application, so the interruption application of interrupt source 211 has just been lost; Because regularly retransmission unit 124 has been arranged, so the interruption application of interrupt source 211 sends out after a while at timing retransmission unit 124 back warps again, if Interrupt Process unit 23 does not respond the interruption application of interrupt source 211; Regularly retransmission unit timing once more behind repetition cycle, is sent application once more, is interrupted processing unit 23 up to this interruption and accepts.Regularly the repetition cycle time interval of retransmission unit 124 can be controlled according to the demand of system by software.
As shown in Figure 6, after the interruption application of interrupt control unit 12, increase a delay unit 121 earlier, increase a regularly retransmission unit 124 again.When interrupt source 210 takes place to interrupt, interrupt the application time-delay of process delay unit 121 earlier, then, directly arrive 23 places, Interrupt Process unit, if Interrupt Process unit 23 does not have the interruption of responsor interrupt source 210, regularly retransmission unit 124 will timing, wait regularly the repetition cycle time to arrive after, send interrupt request to Interrupt Process unit 23 once more, responded up to this interruption.
As shown in Figure 7, interrupt generating unit 20 and interrupt source can be divided into different groups, interrupt in the generating unit 20 the interruption generating unit being arranged, interrupt flag register is also arranged at this.Wherein interrupt register 240 correspondences are with interruption generating unit 201, other and the like, newly-generated interrupt flag register 240 and interrupt register 241 are combined again form last interrupt flag register 24 then, read for interrupting application 120.
With Fig. 8 is example, and the interrupt control disposal route is described.At first, have no progeny in the generation, produced and interrupted application; Interrupt application through after the delay process, whether the device inquiry to Interrupt Process can handle this interruption, after obtaining certainly, just directly enter the handling procedure of interruption, if do not meet with a response, just enter regularly retransmission process, just send once application to the Interrupt Process unit every a timing repetition cycle, can be processed up to this interruption.
The above only is the preferable embodiment of the present invention, can obtain new application by some changes, so concrete protection domain is as the criterion with claim.
Claims (15)
1, a kind of interrupt control treating apparatus is characterized in that comprising:
Interrupt generating unit comprises one or more interrupt sources, is used for producing interrupting;
Interrupt flag register, the interruption that described interrupt generating unit is sent is stored in the corresponding interrupt flag register;
The interrupt control unit is combined to form the interruption application through all interrupt identifications and gives the Interrupt Process unit, handles;
The Interrupt Process unit is used to accept the interruption application that described interrupt control sieve unit selects and handles.
2, interrupt control treating apparatus according to claim 1, it is characterized in that: also include a delay unit in the interrupt control unit, be used for the interruption application that receives is reasonably postponed, give enough processing times of described Interrupt Process unit, guarantee that interruption application afterwards is not dropped.
3, interrupt control treating apparatus according to claim 2 is characterized in that: the delay time of described delay unit can use software to be provided with according to system's needs at interval.
4, interrupt control treating apparatus according to claim 3 is characterized in that: described delay time can be set to 0 at interval.
5, according to arbitrary described interrupt control treating apparatus in the claim 2,3 or 4, it is characterized in that: described delay unit can be set to use or do not use.
6, interrupt control treating apparatus according to claim 1, it is characterized in that: also comprise a timing retransmission unit in the described interrupt control unit, be used for not retransmitted, make this interruption application constantly send to described Interrupt Process unit by the interruption application of described Interrupt Process cell response.
7, interrupt control treating apparatus according to claim 6 is characterized in that: the timing repetition cycle of described timing retransmission unit can use software to be provided with according to system's needs.
8, interrupt control treating apparatus according to claim 1 is characterized in that: also dispose a FIFO buffer between described interrupt generating unit and interrupt flag register, be used to preserve and be not interrupted the interruption that flag register is deposited.
9, interrupt control treating apparatus according to claim 1 is characterized in that: described interrupt source is original interrupt source or non-original interrupt source, is implemented as follows:
The back of dividing into groups, a plurality of original interrupt source is formed different elementary interrupt generating unit, and described elementary interrupt generating unit can be assigned with uses an elementary interrupt flag register;
Then with above-mentioned elementary interrupt flag register as new " interrupt source ", non-original interrupt source forms described interrupt generating unit.
10, interrupt control treating apparatus according to claim 9 is characterized in that: can divide into groups according to the feature in original interrupt source, come the probability or the importance of the interruption generation of balanced each group.
11, interrupt control treating apparatus according to claim 10 is characterized in that: the feature in described original interrupt source includes but not limited to following feature: the importance of interruption, the frequency and this interrupt routine that interrupt taking place occupy the Interrupt Process unit time.
12, a kind of interrupt control disposal route is characterized in that, this method may further comprise the steps:
A produces interruption;
The interruption that B will produce deposits in the interrupt flag register, forms interrupt identification;
C utilizes the interrupt control unit, all interrupt identifications is combined to form interrupts applying for offering the Interrupt Process unit;
This interruption application is accepted in D Interrupt Process unit, enters the program of handling interrupt, and next step that finish that this interruptions applies for by the Interrupt Process unit judges whether to carry out this interrupt handling routine.
13, according to the described interrupt control disposal route of claim 12, it is characterized in that: among the described step C, before giving the Interrupt Process unit, can make certain delay process this interruption application with interruption.
14, according to the described interrupt control disposal route of claim 13, it is characterized in that: whether described delay process can be selected to carry out.
15, according to the described interrupt control disposal route of claim 12, it is characterized in that step C executes, when interrupting not, this is interrupted application make regularly retransmission process, should interrupt application up to the Interrupt Process cell processing by described Interrupt Process cell response.
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| CNB2005101256590A CN100365604C (en) | 2005-12-02 | 2005-12-02 | Interrupt control handling apparatus and method |
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| CNB2005101256590A CN100365604C (en) | 2005-12-02 | 2005-12-02 | Interrupt control handling apparatus and method |
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Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100578480C (en) * | 2007-07-12 | 2010-01-06 | 华为技术有限公司 | Interrupt processing method and device |
| CN101937364A (en) * | 2009-06-30 | 2011-01-05 | 华为技术有限公司 | A method and device for interrupting synthesis |
| CN102067083B (en) * | 2008-06-27 | 2013-12-04 | 微软公司 | Lazy handling of end of interrupt messages in a virtualized environment |
| CN103544125A (en) * | 2012-07-12 | 2014-01-29 | 深圳市中兴微电子技术有限公司 | Interrupt control method, interrupt processing method, interrupt controller and processor |
| CN104380246A (en) * | 2012-06-15 | 2015-02-25 | 国际商业机器公司 | Program Interrupt Filtering in Transaction Execution |
| CN105468497A (en) * | 2015-12-15 | 2016-04-06 | 迈普通信技术股份有限公司 | Interruption exception monitoring method and apparatus |
| CN106569889A (en) * | 2016-11-09 | 2017-04-19 | 上海斐讯数据通信技术有限公司 | Interrupt processing system and method |
| CN108549578A (en) * | 2017-12-25 | 2018-09-18 | 贵阳忆芯科技有限公司 | A device and method for interrupting polymerization |
| US10185588B2 (en) | 2012-06-15 | 2019-01-22 | International Business Machines Corporation | Transaction begin/end instructions |
| US10353759B2 (en) | 2012-06-15 | 2019-07-16 | International Business Machines Corporation | Facilitating transaction completion subsequent to repeated aborts of the transaction |
| US10558465B2 (en) | 2012-06-15 | 2020-02-11 | International Business Machines Corporation | Restricted instructions in transactional execution |
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| CN113986789A (en) * | 2021-09-19 | 2022-01-28 | 山东云海国创云计算装备产业创新中心有限公司 | Method for preventing interrupt loss and interrupt controller |
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| US6192442B1 (en) * | 1998-04-29 | 2001-02-20 | Intel Corporation | Interrupt controller |
| US6845419B1 (en) * | 2000-01-24 | 2005-01-18 | Freescale Semiconductor, Inc. | Flexible interrupt controller that includes an interrupt force register |
| KR100817047B1 (en) * | 2004-02-27 | 2008-03-26 | 삼성전자주식회사 | Interrupt controller |
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2005
- 2005-12-02 CN CNB2005101256590A patent/CN100365604C/en not_active Expired - Fee Related
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| CN100578480C (en) * | 2007-07-12 | 2010-01-06 | 华为技术有限公司 | Interrupt processing method and device |
| CN102067083B (en) * | 2008-06-27 | 2013-12-04 | 微软公司 | Lazy handling of end of interrupt messages in a virtualized environment |
| CN101937364A (en) * | 2009-06-30 | 2011-01-05 | 华为技术有限公司 | A method and device for interrupting synthesis |
| US10719415B2 (en) | 2012-06-15 | 2020-07-21 | International Business Machines Corporation | Randomized testing within transactional execution |
| US10437602B2 (en) | 2012-06-15 | 2019-10-08 | International Business Machines Corporation | Program interruption filtering in transactional execution |
| US10684863B2 (en) | 2012-06-15 | 2020-06-16 | International Business Machines Corporation | Restricted instructions in transactional execution |
| US10606597B2 (en) | 2012-06-15 | 2020-03-31 | International Business Machines Corporation | Nontransactional store instruction |
| US10599435B2 (en) | 2012-06-15 | 2020-03-24 | International Business Machines Corporation | Nontransactional store instruction |
| CN104380246B (en) * | 2012-06-15 | 2017-10-24 | 国际商业机器公司 | Method, system and medium for the interruption in managing computing environment |
| CN104380246A (en) * | 2012-06-15 | 2015-02-25 | 国际商业机器公司 | Program Interrupt Filtering in Transaction Execution |
| US10185588B2 (en) | 2012-06-15 | 2019-01-22 | International Business Machines Corporation | Transaction begin/end instructions |
| US10353759B2 (en) | 2012-06-15 | 2019-07-16 | International Business Machines Corporation | Facilitating transaction completion subsequent to repeated aborts of the transaction |
| US10430199B2 (en) | 2012-06-15 | 2019-10-01 | International Business Machines Corporation | Program interruption filtering in transactional execution |
| US11080087B2 (en) | 2012-06-15 | 2021-08-03 | International Business Machines Corporation | Transaction begin/end instructions |
| US10558465B2 (en) | 2012-06-15 | 2020-02-11 | International Business Machines Corporation | Restricted instructions in transactional execution |
| CN103544125B (en) * | 2012-07-12 | 2017-02-22 | 深圳市中兴微电子技术有限公司 | Interrupt control method, interrupt processing method, interrupt controller and processor |
| CN103544125A (en) * | 2012-07-12 | 2014-01-29 | 深圳市中兴微电子技术有限公司 | Interrupt control method, interrupt processing method, interrupt controller and processor |
| CN105468497A (en) * | 2015-12-15 | 2016-04-06 | 迈普通信技术股份有限公司 | Interruption exception monitoring method and apparatus |
| CN106569889A (en) * | 2016-11-09 | 2017-04-19 | 上海斐讯数据通信技术有限公司 | Interrupt processing system and method |
| CN108549578A (en) * | 2017-12-25 | 2018-09-18 | 贵阳忆芯科技有限公司 | A device and method for interrupting polymerization |
| CN111625175B (en) * | 2020-05-06 | 2021-06-22 | Oppo（重庆）智能科技有限公司 | Touch event processing method, touch event processing device, medium and electronic equipment |
| CN111625175A (en) * | 2020-05-06 | 2020-09-04 | Oppo（重庆）智能科技有限公司 | Touch event processing method, touch event processing device, medium and electronic equipment |
| CN113986789A (en) * | 2021-09-19 | 2022-01-28 | 山东云海国创云计算装备产业创新中心有限公司 | Method for preventing interrupt loss and interrupt controller |
| CN113986789B (en) * | 2021-09-19 | 2024-04-23 | 山东云海国创云计算装备产业创新中心有限公司 | Method for preventing interrupt loss and interrupt controller |
| CN118760639A (en) * | 2024-09-06 | 2024-10-11 | 上海芯力基半导体有限公司 | An interrupt processing module, method, bridge chip and multi-core processor system |
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