JPH08221247A - Data processing device - Google Patents

Abstract

(57) [Summary] [Object] A data processing device for reading / writing a continuous bit string from an arbitrary bit boundary, and an object of the present invention is to provide a data processing device capable of high-speed bit string extraction with a relatively simple configuration. To do. [Structure] 2 consecutive from the data bus 15 of the MPU 11
A buffer register 17 for fetching and holding data of bytes, a multiplexer unit 18 for selecting a desired continuous bit string from the buffer register 17 according to an address from the address bus 16 of the MPU 11, and a data selected by the multiplexer unit 18 By masking with the preset mask data, only the bit string of the necessary portion is taken out and the data bus 1 is stored as 1-byte data.
5, and an output circuit 19 for outputting to 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device,
In particular, the present invention relates to a data processing device that reads / writes a continuous bit string from an arbitrary bit boundary. In recent years, with the development of data compression processing, it has been required for an information processing apparatus to handle data of a variable length bit string.

A microprocessor (MPU), which is the core of an information processing apparatus, is designed mainly for handling data in 1-byte units. However, there are many requests to perform a large amount of bit-wise processing. For example, the MH (Mod that is used when a facsimile machine transfers an image)
if huffman), MR (modify)
d READ), MMR (moderated MR)
In a data compression method called a data compression, the minimum unit of data is a variable-length bit string, and when encoding / decoding, it is necessary to extract a bit string having a different length from a different bit boundary. Processing of several steps to several tens of steps is required. That is, the processing speed is reduced.

To increase the processing speed with such a device,
It is necessary to extract the required bit string from the bit boundary at high speed.

[0004]

2. Description of the Related Art Conventionally, a 1-byte 8-bit unit MPU
When performing data compression or the like, in the case of taking out bit strings of different lengths from different bit boundaries, the processing is executed by software by a program.

When performing such processing, the MPU is set to 1
Since data can be handled only in units of bytes and 8 bits, first, 1-byte data including a required bit string is read, a required bit string is taken out and held as 1-byte data. Next, read the next 1 byte of data that is consecutive to the 1 byte of data that was previously read,
A bit string that is continuous with the previously fetched bit string is fetched and held as 1-byte data, and 1-byte data including the previously fetched required bit string portion and the next fetched required bit string portion are included. The necessary bit string was taken out by synthesizing the data and 1-byte data.

[0006]

However, in the conventional data processing apparatus, when extracting bit strings of different lengths from the bit boundary, the processing is performed by controlling the program of the MPU in order to reduce costs and change the functions. In general, an MPU designed to handle data in 1-byte units requires several to several tens of steps in order to extract an arbitrary bit string, which makes it difficult to speed up the processing. There was a problem.

When it is necessary to increase the processing speed, it is possible to perform the processing by hardware such as a dedicated LSI, and in the case of the above MH, MR and MMR, the encoding /
Although many LSIs and the like that perform decoding have been commercialized, the cost becomes high, and once designed, there are problems that it is not easy to change functions and it is difficult to deal with design failures.

The present invention has been made in view of the above points, and an object of the present invention is to provide a data processing device capable of high-speed processing of bit string extraction with a relatively simple structure.

[0009]

FIG. 1 shows the principle of the present invention. The data processing means 1 selects a desired bit string and performs a predetermined process in a data processing device which extracts a continuous bit string from an arbitrary bit boundary.

The bit boundary holding means 2 holds a bit boundary including a bit string processed by the data processing means. The selection means 3 is supplied with the data of each bit of the bit boundary held in the boundary holding means, and selects consecutive bit strings according to the selection signal supplied from the data processing means to the desired bit string. Output.

A third aspect of the present invention has masking means for masking unnecessary bits from the bit string selected and output by the selecting means.

[0012]

According to the first aspect of the present invention, the process of extracting a continuous bit string from an arbitrary bit boundary can be performed by the bit boundary holding means and the bit string selecting means, and the data processing means can obtain the required bit string. It is possible to obtain the required bit string only by supplying the selection signal that selects the required bit string from the included bit boundary and the bit boundary, so that the processing load on the data processing means can be reduced and the data processing can be performed efficiently. It

According to the second aspect of the present invention, the bit boundary holding unit and the bit string selecting means are composed of dedicated hardware, whereby the bit string can be extracted at high speed. According to the third aspect, since the unnecessary bit portion in the extracted bit string can be cut by providing the mask means, only necessary data can be extracted.

[0014]

1 is a block diagram of a first embodiment of the present invention. The data processing device 10 of the present embodiment is the data processing means 1
MPU (microprocessor unit) 11 that becomes, a bit string extraction circuit 12 that extracts a desired bit string from an arbitrary bit boundary, a memory 13 that stores data processed or to be processed by the MPU 11, and data to be processed by the MPU 11 are input In addition, the input / output (I / O) unit 14 outputs the data processed by the MPU 11.

The MPU 11, bit string extraction circuit 12, memory 13, and input / output unit 14 are connected by a data bus 15, an address bus 16 and a control line (not shown). The MPU 11 takes in a bit string containing the data to be processed and, as will be described later, the bit string extraction circuit 12
And a required bit string is taken out from the bit string extraction circuit 12 according to the selection signal, and if it is a data compression process, a process such as encoding / decoding is performed.

The bit string extraction circuit 12 is provided with a buffer register 17 capable of storing a bit boundary of 2 bytes, each bit of the buffer register 17 is connected, and a multiplexer 18 and a multiplexer 18 for selecting a continuous bit string according to an address from the MPU 11. An output circuit 19 for outputting the selected data to the data bus 15 and a timing control unit 20 which is supplied with an address and generates various timings according to the address.

The buffer register 17 is composed of an even data register 17-1 and an odd data register 17-2 which can store 1 byte of data. Continuous bit boundaries are stored in the even data register 17-1 and the odd data register 17-2.

FIG. 3 is a block diagram of the bit string extraction circuit 12 of the first embodiment of the present invention. The timing control unit 20 is connected to the address bus 16 and
An address decoder 21 which outputs a signal which becomes high or low according to an address supplied from each address,
An OR gate 22 that ORs the signals of the address decoder
It is composed of

The address decoder 21 has an output corresponding to a predetermined address. Among the addresses supplied from the address bus 16, the addresses 0 to F (hexadecimal number) are supplied to the OR gate 22, and the address 10 is supplied. The data holding control signal EVENDA is set to the even-numbered data register 17-1 and the address of 11th address to the odd-numbered data register 17-2.
The address of address 12 is supplied to the mask register 19-2 of the output circuit 19 as TA REG, ODD DATA REG and as a mask control signal.

As for the output of the address decoder 21, only the output corresponding to the address supplied from the address bus 16 is set to the high level. The OR gate 22 is the address decoder 2
The logical sum of the outputs corresponding to the addresses 0 to F of the output of 1 is calculated and supplied to the shift register 19-3 of the output circuit 19.

The even-numbered data register 17-1 receives the data holding control signal EVEN DAT from the address decoder 21.
AREG is supplied and 8-bit data is supplied in parallel from the data bus 15. The even data register 17-1 receives the 8-bit (1 byte) data supplied from the data bus 15 from the address decoder 21 and holds the data holding control signal EVEN DATA REG.
And is supplied to the multiplexer unit 18.

The odd data register 17-2 has a data holding control signal ODD D from the address decoder 21.
ATA REG is supplied and 8-bit data is supplied in parallel from the data bus 15. The odd-numbered data register 17-2 receives the 8-bit (1 byte) data supplied from the data bus 15 from the data hold control signal ODD DATA RE supplied from the address decoder 21.
It is held according to G and supplied to the multiplexer unit 18.

The multiplexer unit 18 is composed of eight multiplexers 18-1 to 18-8 having 16-bit inputs, and the 8-bit data from the even-numbered data register 17-1 and the odd-numbered data register 17-2 is stored in the multiplexer unit 18. The signals are input while being sequentially shifted for each of the multiplexers 18-1 to 18-8 so as to be continuous.

The multiplexers 18-1 to 18-8 are connected to the address ADRS for the lower 4 bits from the address bus 16.
0 to ADRS3 are supplied, and any one of the input bits Bit0 to Bit15 is selected according to the supplied address. For example, when the bit Bit0 is selected, the data DATA0 to DATA0 of the even data register 17-1
7. Data DATA0 to Odd data register 17-2
When continuous 1-byte data is selected in the order of 7 and bit Bit1 is selected, data 1 to 7 in the even-numbered data register 17-1 and data DATA0 in the even-numbered data register 17-1 are consecutively written in the order of 1-byte data. The data is selected, starting with different bits depending on the selected bit,
It is configured to obtain a continuous bit string.

The bit string selected by the multiplexer unit 18 is supplied to the AND gate 19-1. The AND gate unit 19-1 is the multiplexer 1 of the multiplexer unit 18.
8-1 to 18-8 are provided, and mask registers 19 are provided in addition to the outputs of the multiplexers 18-1 to 18-8.
-2 has been entered. The AND gate 19-1 discards an unnecessary bit portion by performing a logical product of each bit selected by the multiplexer unit 18 and each bit of the mask data preset in the mask register 19-1 to reject the unnecessary bit portion. -3.

The shift register 19-3 holds and outputs the output of the AND gate section 19-1 according to the mask control signal MASK REG of the address decoder 21. FIG. 4 shows an operation flowchart of the first embodiment of the present invention. MPU1
In the case of 1, the source address (so
urce Adrs) register and a bit pointer (bit pointer) that stores the bit position of the bit string to be extracted from the original data with the number of bits counted from the beginning of the original data (step S1).
-1).

Next, the MPU 11 stores data of 2 bytes from the source address stored in the source address register in the even data register and the odd data register,
The latest stored data information (ev) for incrementing the address stored in the source address register by 2 and identifying which of the data stored in the even data register and the odd data register is the latest data (ev od fiag)
Is set to "odd number" indicating that the latest data is stored in the odd number data register (step S1-2).

Next, the MPU 11 checks whether the data string extraction position set in the bit pointer is on the odd shift register side or the even shift register side. This is to check whether the quotient obtained by dividing the value set in the bit pointer by 8 is “even” or “odd” (that is, whether the third bit is 0 or 1), and the latest stored data information ev od This is performed by comparing with the flag (step S1-3).

Here, the latest stored data information ev od
If the flag and the third bit of the quotient obtained by dividing the value of the bit pointer by 8 are different, the latest stored data information is 0.
If so, the next data is stored in order from the odd data register to the source address or 2 bytes worth of data. If the latest stored data information is 8, then the data from the even data register is 2 bytes worth of the source address. The data are sequentially stored (step S1-4).

Next, the MPU 11 adds the source address 1 and updates the latest data information (step S1-
15). If the quotient when the value of the bit pointer is divided by 8 in step S1-3 is the same as the latest stored data connection, the processes of steps S1-4 and S1-5 are omitted and step S1-6 is performed. The process of is executed.

Next, the MPU 11 takes out the data from the shift data registers 0 to 15 according to the value (0 to 15) of the lower 4 bits of the bit pointer (step S1-6).
If the data is compressed, the MPU 11 performs encoding / decoding processing on the extracted data (step S1-
7). In the case of continuing the processing, the value of the bit pointer is advanced by the number of bits used for the processing in the extracted bit string, and steps S1-3 to S1-7 are repeated (step S1-8).

The MPU 11 first initializes various built-in variables as follows. Source address source adrs = $ 8000 bit pointer bit pointer = 0 latest stored data information ev of flag = 0 bit pointer bit Third bit of pointer and latest stored data information ev od Since it is equal to 0 with the third bit of flag, step S1-6 is executed.

Bit pointer bit Since the lower 4 bits of the pointer are "0000" (= 0), one byte is taken out from "shift data register 0". The data taken out is '00101101'. Processing is performed according to the taken-out data '00101101'.

Here, it is assumed that, as a result of decoding 8 bits from the beginning, only 5 bits "00101" from the upper bits are used. Bit number actually used = 5 bit inter-bit Add to pointer.

Bit pointer bit Third bit of pointer and latest stored data information ev od fla
The third bits of g are both 0 and are equal. Bit pointer bit The lower 4 bits of the pointer are "0101"
Since (= 5), one byte is taken out from the "shift data register 5". The retrieved data is' 10111
The process which is 001 'is performed.

Here, from the above, 4 bits "1011"
To use. Number of bits actually used = 4 bit p
Add to Ointer. Bit pointer bit po
Bit 3 of inter is 1. ev od f
Bit 3 of lag is 0, which is different. For this reason,
Dress source fetch 1 byte from adrs
(Content $ C6 of $ 8002 is retrieved).

Latest stored data information ev od flag
Is 0, the fetched data is stored in the "even data register". Source address source adr
Add 1 to s, source address source adr
It becomes s = $ 8003.

Latest stored data information ev od flag
To update. Latest stored data information ev od flag
= 8. Bit pointer bit Since the lower 4 bits of the pointer are "1001" (= 0), one byte is taken out from the "shift data register 9". The extracted data is '10010011'.

Processing is performed. Here, 4 bits '1001' are used from the above. Number of bits actually used = 4
The bit pointer bit Add to pointer.

Bit pointer bit pointer
The third bit is 1. ev od Flag of flag
Since step 3 is 0, which is different, step S1-4 is executed.
It FIG. 6 shows an example of a memory map of addresses. Figure 7
In the example of actually reading and writing data, the original data
If there is {$ 68, $ 5C, $ 15, ...}, the first
2 bytes for even data register and odd data register
When each shift register is read when set to
Indicates the value of. Like this from any bit boundary
It can be seen that the data can be read in 8-bit units. Also a mask
Remove extra bits by changing register settings
It is also possible to read a bit string with 7 bits or less.
It

In this example, from "bit boundary 0: shift data register" to "bit boundary 7: shift data register", continuous bit strings from the beginning of the original data are obtained, but "bit boundary 8: shift data register" is obtained. When reading from "register" to "bit boundary F: shift data register", a correct bit string cannot be obtained. When accessing these registers, the 3rd byte ($ 15) of the original data is stored in the even data register.
Set. That is, when a bit string starting from the 0th to 7th bits of the original data is used, the 1st and 2nd bytes of the original data are written to the even data register and the odd data register respectively, and the 8th to 8th bits of the original data are written.
When using the bit string starting from the 15th bit, the even data register and the odd data register are
The 3rd and 2nd bytes of the original data are replaced with 16
When using a bit string starting from the 23rd bit, the contents of the even data register and the odd data register are as follows: the even data register and the odd data register are the third and fourth bytes of the original data, respectively. It must be updated alternately every time 8 bits are added.

In this embodiment, the register width is all 8 bits, but the register bit width may be changed depending on the MPU used and the processing contents. Further, it is not necessary to match the register size of the original data and the bit width of the shift data register. According to this embodiment, the normal MPU
Is an MPU that can be accessed only in 1-byte 8-bit units, and when the desired bit string is extracted from the MPU in normal 1-byte and 8-bit units at the same speed and at an arbitrary bit boundary. Is possible. In addition, when accessing a next successive bit string after extracting a certain bit string, all that is necessary is to add the bit length of the previously extracted bit string to the address, which simplifies the processing.

It is also possible to write data at an arbitrary bit boundary by reading data from the even-numbered data register 17-1 and odd-numbered data register 17-2 after writing data from the multiplexer 18 side by using the bypass 15a. it can. Further, as described above, the data output from the multiplexer 18 and the mask register 19-
The bit length to be taken out can be changed by performing a logical product with the data stored in 2 and obtaining the result.

FIG. 8 shows a block diagram of the second embodiment of the present invention. 2, those parts which are the same as those corresponding parts in FIG. 2 are designated by the same reference numerals, and a description thereof will be omitted. In this embodiment, the buffer register is not provided and the data is directly read from the memory. Normally, when the address is incremented by 1, the data position to be accessed is incremented by +1 byte, but in the access by the arbitrary bit boundary, the address is incremented by 8 and the access data is changed by +1 byte. Therefore, in the bit boundary access, a virtual memory space that is eight times the physical memory capacity is provided.

The memory 31 is an even data storage memory 32.
The address bus connected to the memory 31 is divided into two kinds of addresses for normal access and arbitrary bit boundary access by the address generator 34, and the multiplexer 35,
Either is selected by 36. The address for normal access is the same as the address obtained from the address bus, but the address at the time of bit boundary access uses the lower-order bits of the address bus in the multiplexer 18
It is rounded down for the select signal of, and the remaining upper address is right-shifted and obtained. The number of bits to be discarded depends on the data bus width of the memory. When the bit boundary access is made to the even data storage memory 32, there is a case where the address is incremented by 1. Therefore, the adder 38 is required. This adder 38 determines whether the address is used as it is or is incremented by one. The multiplexer 18 is similar to that of FIG. 2, and outputs a bit string from the bit boundary determined by adding the upper 1 bit to the bits truncated by the address generator 34. Multiplexer 37
Switches between using the data bus for normal access and the data for bit boundary access.

[0046]

As described above, according to claim 1 of the present invention, the processing for extracting a continuous bit string from an arbitrary bit boundary can be performed by the bit boundary holding means and the bit string selecting means, and the data processing means. Can obtain the required bit string simply by supplying a bit boundary including the required bit string and a selection signal for selecting the required bit string from the bit boundary.
It has features that the processing load on the data processing means can be reduced and the data processing can be performed efficiently.

According to the second aspect of the present invention, the bit boundary holding unit and the bit string selecting means are composed of dedicated hardware, so that the bit string can be extracted at high speed. According to the third aspect, since the unnecessary bit portion of the extracted bit string can be cut by providing the mask means, only necessary data can be extracted and the processing by the data processing means is facilitated. It has features such as being able to.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a block diagram of a first embodiment of the present invention.

FIG. 3 is a block diagram of a bit string extraction circuit according to the first embodiment of the present invention.

FIG. 4 is an operation flowchart of the first embodiment of the present invention.

FIG. 5 is an operation explanatory diagram of the first embodiment of the present invention.

FIG. 6 is an operation explanatory diagram of the first embodiment of the present invention.

FIG. 7 is an operation explanatory diagram of the first embodiment of the present invention.

FIG. 8 is a block diagram of a second embodiment of the present invention.

[Explanation of symbols]

 1 data processing means 2 bit boundary holding means 3 bit string selecting means 10 data processing device 11 MPU 12 bit string extracting circuit 13 memory 14 input / output unit

Claims (3)

[Claims] 1. A data processing device for extracting a continuous bit string from an arbitrary bit boundary, comprising a data processing means for selecting a desired bit string and performing a predetermined process, and a bit including a bit string processed by the data processing means. Holding means for holding a boundary, data of each bit of the bit boundary held by the holding means is supplied, and a continuous bit string according to a selection signal supplied by the data processing means by throwing in the desired bit string. And a selection means for selectively outputting the data processing device. 2. The data processing device according to claim 1, wherein the bit boundary holding means and the bit string selection means are configured by dedicated hardware. 3. The data processing apparatus according to claim 1, further comprising masking means for masking unnecessary bits from the bit string selected and output by the selecting means.