JPH04252487A - Memory - Google Patents

Abstract

PURPOSE: To provide a pipeline structure for serial side to accelerate the speed of serial output from a dual port memory. CONSTITUTION: In order to output the group of data from a register 8 which can transfer the contents of plural cell positions on the rows of a memory array, a selecting means 22 selects any register position corresponding to the data group. The contents of the register 8 are transferred through an intermediate data line to a latch 112. A circuit 116 is provided for separating the next data group from the latch 112 so that the contents of the latch 112 can not be destroyed by the next data group.

Description

[Detailed description of the invention]

0001

FIELD OF INDUSTRIAL APPLICATION The present invention relates to memory devices, particularly dual port memory devices such as those used in graphics applications.
In the field of random access semiconductor memory devices.

0002

BACKGROUND OF THE INVENTION With the advent of less expensive semiconductor memory, modern computer and microcomputer systems are now able to use bitmap video displays for the output of data from the system. Ta. As is well known, bitmap display devices require memory capable of storing at least one binary digit (bit) of information for each picture element (pixel) of the display. Additional bits stored for each pixel allow complex images on a video display device, such as background and foreground images such as multi-color images or graphic backgrounds with structural information on top of them. It provides the possibility for the system to express, etc. By using bitmap storage, data processing operations that easily generate and modify stored images are also contemplated.

Modern video display devices are often of the raster scan type, in which an electron gun traces horizontal lines across the display screen to generate the displayed pattern. In order for the displayed raster scan image to continue to be displayed on the video screen, the image must be refreshed at periodic intervals. A common refresh rate for cathode ray tube (cathode ray tube) video display devices is 1/60th of a second, since refresh operations performed at this rate are not noticeable to human users of the system. However, as the number of pixels displayed on the screen increases, in order to increase the resolution of the displayed image,
More bits of information must be accessed from bitmap memory between refreshes. If this bitmap memory has only one input/output port, and the refresh interval remains constant, the percentage of time that the data processing device can access the bitmap memory is the size of the pixel size of the display device. decreases with Additionally, the speed of the memory must be increased because more bits must be output in a given period of time.

Multi-port random access memories have been developed that provide high speed output of data to video display devices and likewise provide increased access possibilities for the contents of the memory to data processing devices. It is provided to A multi-port memory accomplishes this by including: a first port for random access and updating of the memory by a data processing unit of the computer system;
a second port for serial output of the memory contents to the video display device independently of and asynchronously to the first port, whereby the memory contents are output during output of the data to the video display terminal; This is done by providing access to Examples of multi-port random access memories are U.S. Pat.
Issued on January 27, 1987) and No. 4,636,986
issue (issued January 13, 1987) (both Texas
(Assigned to Instruments, Inc.) (These corresponding Japanese applications have patent publication number 1986.
-216200).

In each of these conventional multiport memories, data is shifted from some or all memory cells in a row of a random access array into a register during a special transfer period. Serial output is then achieved from the registers, but in a manner that is independent of and asynchronous to the random access operations of the data in the array. Serial input possibilities can likewise be provided in such devices with other types of transfer cycles that can shift the contents of serial registers to selected rows of a random access array.

The serial "sides" of these conventional multiport memories have been configured according to a variety of structures. For example, the device described in U.S. Pat. No. 4,639,890 has a shift register as a serial side register;
Serial output begins from a selected cell in the shift register from a tap contained in the shift register. Each serial clock pulse transfers data along the shift register with the output resulting from the tapped shift register cell providing a serial stream of data. Of course, serial input can be accomplished by providing input data to tap points and shifting the input data stream along a shift register. However, if fewer tap points than cells are provided to the shift register of this device, then the serial output (
and input) is compromised.

Greater flexibility in serial input/output origins is provided by the apparatus described in the aforementioned US Pat. No. 4,636,986, in which non-shifting registers contain serially output data. In this arrangement, the counter stores the address from which the serial outputs originate, and the decoder operates in response to the counter, for example, to select one of the register cells from which the serial outputs originate. To provide a serial data stream, each pulse of the serial clock signal causes the counter to increment its stored value and the decoder to successively enable the next register cell accordingly. Serial input is similarly accomplished by increasing the number of register cells that receive serial input bits with a serial clock.

Although the use of counter/decoder structures provides increased flexibility regarding the origin of serial inputs and outputs, the counter and decoder circuits required to select and update the selection of serial register bits have built-in delays. include. For example, to increment the position of a serial register, the counter must increment its contents in response to a serial clock pulse, and the decoder must read the output of the counter before the next serial register cell is selected. must be decoded again. Such delays can be reduced through design and manufacturing techniques and are inherent in this particular structure.

It is therefore an object of the present invention to provide a pipeline structure for the serial side of a dual-port memory to improve the speed of serial output from the memory.

It is a further object of the invention to provide a pipeline in which the pipeline is disabled for serial input so that the serial input data is stored in the appropriate location in the serial register.

It is a further object of the invention to disable the pipeline for output while selecting other locations of the serial register.

Other objects and advantages of the invention will become apparent to those skilled in the art upon reference to the following description, taken in conjunction with the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION The present invention provides a dual-port random access system having a serial register for serial output of data independent of and asynchronous to random access to a memory array. May be stored in memory. A counter and decoder selects the group of register cells from which the serial output will originate and latches the bits of data for that group into the multiplexer. This counter increments its contents in response to each period of the serial clock signal. The least significant bit or bits of the counter are decoded and one bit of a group of bits is selected and applied to the serial output terminal, preventing the entire contents of the counter from being decoded for each serial bit. For serial output, the more significant bits of the counter are updated initially, so the decoder selects the next group of bits to output while outputting the last bit of the previous group. In serial input mode, the more significant bits of the counter can be incremented normally, rather than by the initial update used for the serial output, so that serial input data received by the serial register is stored in the preferred register location. The pipeline may also be destroyed when selecting a new serial register address, so the initial output is not disturbed by the initial increment of the counter.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to FIG. 1, this figure is a functional block diagram of a dual port memory 1 constructed according to the present invention. Similar to the memory of the aforementioned U.S. Pat. No. 4,636,986, which is incorporated herein by reference, the dual port memory 1 includes address signals on lines A0 through A8, clock signals RAS_, CAS_, and SCL.
K, a write enable signal WE_, a transfer enable signal TR_, and a serial output enable signal SOE_. A write mask mechanism is included in dual-port memory 1 so that only a single column address strobe CAS_
Note that port memory 1 receives and uses. Dual port memory 1 has eight random access input/output terminals rather than four like the input/output terminals of the memory of said US Pat. No. 4,636,986.
It has output lines D0 to D7, and the invention described herein is of course applicable to any dual port memory structure or other structure. Thus, dual port memory 1 includes eight arrays 2, each of which contains 128 kilobits of storage, organized in this example into 512 rows and 256 columns. Associated with each array 2 is a sense amplifier bank 4, which provides array 2's dynamic memory
Detection, re-storing of data from and into cells;
and 256 sense amplifiers as is well known in the writing art.

On the random access side, RAM logic 1
6 performs address latching and address decoding as was performed in the memory of the aforementioned U.S. Pat. No. 4,636,986, so that the row address strobe signal R
AS_ and column address strobe signal CAS_, respectively, and address lines A0 through A8 are received. Address line A0
The row address value appearing on A8 to A8 is latched by the row address strobe signal RAS_ and
A row of each array 2 can be selected by the X-decoder 18 in response to the latched row address value on line 19. Similarly, the column address values appearing on address lines A0-A7 are transferred to the column address strobe signal C (since the column address signal on line A8 is not needed to select one of the 256 columns).
latched by RAM logic 16 in response to AS_, and the latched column address value is transferred to RAM logic 16 by line 21.
to a Y-decoder 20, each of the eight arrays 2 having a Y-decoder 20 associated with them. Accordingly, each Y-decoder 20 operates to connect the preferred bit line in the associated array 2 corresponding to the latched column address value to its associated input/output buffer 24.

In addition to the functions described in the aforementioned US Pat. No. 4,636,986, dual port memory 1 provides additional control of random access data entry functions, such as performed by special function logic 30. Has additional controls. Each of the eight input/output buffers 24 is connected through a multiplexer 26 to data terminals D0 through D7. For random access reading, the output of input/output buffer 24 is received by output drive circuit 31 and thereby transmitted to the terminals of lines D0-D7. Output drive circuit 31 is constructed in one of a number of well-known configurations and is enabled by an external signal on line TR_ under control of RAM logic 16. Of course, random
For access writing, the output drive circuit 31
Overridden by logic 16 to prevent data conflicts.

During a write cycle, line WTCLR from special function logic 30 controls multiplexer 26 so that the data values appearing at data terminals D0 through D7 or line 2
The input/output buffer 24 via 7 selects either the contents of the color register 50 in the functional logic 30, depending on the user selected function. Special function logic 30 is also operable to control a write mask mechanism similar to that described above for the aforementioned U.S. Pat. 54, so that the write mask value is operable for multiple periods and after the write mask value is initially loaded and for unmasked random accesses. After a write cycle, any number of cycles can be recalled. The contents of write mask register 54, or the contents of the unmasked write signal, are preferably transferred by special function logic 30 to input/output buffer 24 via line WCLK, as described in the aforementioned Serial No. 053,200 application. Add to.

Referring to the serial side of dual port memory 1, transfer gate 6 is similar to that described in US Pat. No. 4,636.
, 986, is connected to each of the bit lines of array 2 to transfer data from array 2 to data register 8,
Or do the opposite. In this example, data register 8
is a 256-bit register, so 256 bits of data
Bits are transferred for each bank of transfer gates 6, ie 2048 bits of data are transferred in each transfer period. Serial logic 14 includes a serial clock signal on line SCLK,
The serial enable signal on line SOE_ and the transfer signal on line TR_ are received as well as the signals from the RAM logic 16, thus ensuring proper data transfer as in the memory of said U.S. Pat. No. 4,636,986. can be executed at any time.

As will be explained in more detail below, the counter 22, which may also include a pre-decoder,
Select one bit in each data register 8 to which serial input/direct output is to be initiated. Thus, counter 22 receives a latched column address signal from RAM logic 16 on line 21, and for the memory of the '986 patent, that signal is either serial input or serial output starting. Select the position in series that will be the same. Serial logic 14 controls counter 22 to load the latched column address value during the transfer period and provides a signal to counter 22 for each period of the clock signal on line SCLK to load the latched column address value to counter 22. Allow the stored value to increase with each series cycle. In this embodiment, counter 22 further includes a predecoder that partially decodes the values stored therein. Each serial decoder (or pointer) 10, as associated with each data register 8, receives the partially decoded contents of counter 22. The contents of data register 8 are not shifted therein each serial period as in the memory of said U.S. Pat. No. 4,636,986, but instead serial decoder 10 indicates one bit therein. , the position of that bit will increase with each period of the clock signal on line SCLK that increments the contents of counter 22. The contents of the bits of each data register 8 indicated by an associated one of the serial decoders 10 are connected for input and output to an associated one of the serial input/output buffers 12 and connected to said serial input/output buffers 12 for input and output. One of the output buffers is 8
associated with each of the arrays 2 and data registers 8. A serial input/output buffer 12 connects the associated serial input/output terminals SD0 to SD7 and the serial decoder 10.
The bits of the associated data register 8 indicated by .

Terminal SOE_ is a serial input/output terminal SD
Signals are received during various stages of the memory cycle to place SD0 through SD7 into serial input mode or serial output mode. In the device of FIG. 1, execution of a memory-to-register transfer cycle automatically places the serial side in serial output mode. Since in the serial output mode a high logic level on the line SOE_ disables the serial output and a low logic level on the line SOE_ enables the serial output, the signal received by the terminal SOE_ is output enable controlled in a manner well known in the art. used for.

In order to switch the serial side of the dual port memory 1 from serial read mode to serial write mode, a pseudo transfer cycle is performed. Terminal RAS_, WE_, T
The signals provided on R_, and SOE_ are used to perform and set up this cycle as well as to perform a transfer operation. Referring to Table 1, the truth table of these signals during the high-to-low transition of RAS_ is illustrated with respect to performing transfers in both directions and the pseudo-transfer period that sets up the serial input mode.

[0022]

[Table 1] ────────────────────────
────────────
Table 1
TR_WE_SOE_
Period ---
−−− −−−− −−−
−−−−−−−−−−− 0
0 0
Transfer from register to memory 0
0 1
Setup serial input mode 0
1 X
Transfer from memory to register;

Setup serial output mode ────────────────────────
────────────RAS_Transition line A0 to A
Note that the value of the row address signal on 8 is used to select the row from or to which the register transfer will occur. Set serial input mode
In the rising pseudo-transfer period, the memory cells of the addressed row are refreshed. Once in serial input mode, a high logic state of terminal SOE_ disables serial input at terminals SD0 to SD7, and a low logic state of terminal SOE_ enables serial input there. Therefore, in serial input mode, SOE_ performs an input enable function.

Referring now to FIG. 2, the construction and operation of counter 22 and serial decoder 10 in accordance with a first preferred embodiment of the invention will now be described in more detail in conjunction with data register 8. Regarding the serial decoder 10 and data register 8, the serial input/output terminals SD0 to SD
The following explanation is related to one of the series input/output terminals SD.
It should be understood that it is also repeated for each of 0 through SD7.

Counter 22 is a ripple counter,
eight presettable T-shaped latches 100n for storing the address value of one bit out of the 256 bits of data register 8 that is to be output (or in which input data is to be stored); include. Each of the latches 100n preferably has both true and complement T (toggle) inputs and true and complement Q outputs. Each latch 100n receives a signal line PS from RAM logic 16 in conjunction with a load enable signal on line LDEN.
Set in advance from 0 to PS7, and use serial input/
It may be possible to load the first position of the data register 8 for output into it. As previously discussed, this initial value is selected by the column address signals on lines A0-A8 during the transfer period. After presetting, line LDEN returns to the inactive state and latch 100n is no longer responsive to logic states on lines PS0-PS7.

Latch 100n is such that the content stored therein is determined by a low-to-high transition at its T input (ie, at its T input).
It is T-shaped and toggles in response to a high-to-low transition on the input. Latch 1000 stores the least significant bit of counter 22 and toggles its contents in response to a serial clock signal received at terminal SCLK. latch 10
01 and latches 1003 to 1007 are T_
It receives the Q output from the previous latch at its input, thus latch 1000 and latches 1002 to 1.
When the content of one of 006 changes from 1 to 0,
The contents of the next top of latches 100n are toggled to enable the carry, thereby causing counter 22
The value stored in is increased correctly. Q of latch 1001
A multiplexer 102 is connected between the T and T_inputs of the latch 1002 and the T and T_inputs of the latch 1002.
001 output or NAND to latch 1002
Select one of the outputs of gate 104. Multiplexer 102 is controlled by a signal SI from serial logic 14, which signal SI determines whether the serial side of dual port memory 1 is in serial input mode or serial output mode, as selected according to Table 1 above. Show if there is. In series output mode, as explained in more detail below,
To keep the serial output data pipeline full, the true and complement outputs of NAND gate 104 are connected to the T and T inputs of latch 1002 to
Expect a carry from 01 to latch 1002. In serial input mode, the true and complement outputs of latch 1001 are connected to the T and T_inputs of latch 1002, as well as the interconnections of the other latch 100n of counter 22.

The two least significant bits of the stored address value, stored in latches 1000 and 1001, are decoded in counter 22 by LSB decoder 110, and one of the four lines PMX0 to PMX3 is Driven to a high logic level in response to the values stored in latches 1000 and 1001. For example, the line PMX0 has the value 0
Driven high by LSB decoder 100 in response to latches 1000 and 1001 storing a zero, line PMX
1 is driven high in response to the value 01 stored therein, and so on. Therefore, lines PMX0 to P
The high logic levels driven on MX3 do not overlap in time because only one level is active and the other levels are excluded. Lines PMX0 to PMX3 control the multiplexer 124 to input the data selected by the predecoder 108 and serial decoder 12, which will be described next, for each data register 8 in the dual port memory 1.
Select 1 bit out of 4 bits of register 8.

Line PMX3 connects latches 1000 and 10
01 carries a high logic level only when it contains the value 11, and N
It is connected to the first input of AND gate 104. NA
A second input of ND gate 104 receives the logical complement of line LDEN (via inverter 111);
allows loading of new values from lines PS0 to PS7 into latch 100n when in a high logic state. Once a new value is loaded and the serial output or input begins, line LDEN goes to a low logic level, thereby changing the logic state of line PMX3 to NAND gate 104.
output can be controlled. NAND gate 104
The outputs of both true and complement (inverted by inverter 105) are provided to multiplexer 102. In series output mode, multiplexer 102 has N
Latch 10 (without inverting) the output of AND gate 104
The output of the inverter 105 is connected to the input T_ of the latch 1002. Therefore, in series output mode, latch 1002
and 1001 increases from the value 11 to the value 00 (the Q and Q outputs of latch 1001
2), it toggles when the contents of latches 1000 and 1001 increase to the value 11.

The six most significant bits of the contents of counter 22 are stored in latches 1002 - 1007 and decoded by predecoder 108 contained within counter 22 . The address stored in counter 22 is added to each of the eight data registers 8 in dual port memory 1, so that rather than completely decoding the same value at eight locations in memory, It is useful to perform at least a partial decoding of this address within the counter 22. Of course, the number of outputs from predecoder 108 varies depending on the number desired to be predecoded in counter 22; for example, predecoder 108 has at its output four of the outputs of latches 1004-1007.
can provide decoding from latch 1 to 16
The output states of 002 and 1003 are the predecoder 10
Pass 8. Thus, the serial decoder 10 associated with each of the data registers 8 is a pre-decoder 108.
in response to the output from its associated data register 8.
is operable to select 4 of the 256 locations. If desired, an intermediate output buffer may be provided to provide buffered data from among four selected locations in data register 8, as is well known in the art. Such intermediate output buffers are not specifically shown in FIG. 2 for the sake of clarity.

In the case of serial output, the contents of the four data registers 8 selected by the serial decoder 10 are
It is connected to the 4-bit latch 112 by transistor 114 and pass transistor 116. Although only one pass transistor 114 and 116 is shown in FIG. 2 for clarity, pass transistor 114 parallel to pass transistor 116 as well as data register 8
and for each of the four data lines between latch 112. Bidirectional tristate buffers are of course also included in the pass transistors 114 and 116 if desired.
May be used instead of. The gate of pass transistor 114 is controlled by the output of OR gate 113;
At the input of that OR gate are the lines SI and LDEN.
There is. Therefore, during series output mode (line SI is low)
, a low logic level on line LDEN causes transistor 11 to
4 is made non-conductive. Except for times when a new value is being loaded into latch 100n, line LDEN is in such a low state and pass transistor 116 is connected to data transistor 8 during the series output, as will be explained in more detail below.
The communication of data between the latch 112 and the latch 112 can be controlled. The gate of pass transistor 116 is controlled by the Q output of RS latch 118;
The set input of 8 is controlled by line PMX0. The reset input to latch 118 is controlled by the output of OR gate 120, whose second input is connected to the output of AND gate 122. AND gate 12
The inputs of 2 are connected to lines PMX3 and LDEN. During series input, the high state of line SI causes latch 118
Pass transistor 114 will communicate data between latch 112 and data register 8 regardless of the state of .

Latch 112 is a 4-bit latch that is connected (via either pass transistor 114 or 116) between data register 8 and 4-to-1 multiplexer 124. to store the data to be communicated. Multiplexer 124 connects line PMX0
to PMX3, and those lines are connected to latch 11.
Which of the 4 bits of 2 is the serial input/output terminal SDn?
(or which of the four bits of latch 112 stores the input data from serial input/output terminal SDn). The necessary input and output buffers are constructed in a well known manner and are connected between the output of multiplexer 124 and the serial input/output terminal SDn.

Now, with reference to FIG. 3, the operation of the circuit of FIG. 2 in the serial output mode will be described. A first example of such operation starts from an initial state in which the contents of latches 1000 and 1001 increase from the previous address to the value 00, and an example of the circuit operation when a new address is loaded into counter 22 is shown below. Explain. Therefore, line LDEN is at a much lower logic level in this example, rendering pass transistor 114 non-conducting and causing the output of AND gate 122 to be at a low logic level. Additionally, line SI at the control input to multiplexer 102 connects T and T_ of latch 1002 to
The output of NAND gate 104 will be selected to be connected to the input. The value 00 of latches 1000 and 1001 causes the LSB decoder 11 to
High logic level on line PMX0 from 0 and PMX1
, PMX2, and PMX3. A high level on line PMX0 sets RA latch 118 (as shown by line Q118 in FIG. 3), connects data register 8 to latch 112, and transfers the contents of the four locations addressed by latches 1002 through 1007. Load. A high logic level on line PMX0 causes multiplexer 124 to select the corresponding one of the four bits of latch 112 for output to serial input/output terminal SDn (designated BIT0 in FIG. 3). I will do it.

The state of latch 1000 is zero upon the next low-to-high transition of the serial clock signal at terminal SCLK.
Toggle from to 1. Since the Q output of latch 1000 is connected to the T input of latch 1001, the T input of latch 1001 will experience a high to low transition, preventing latch 1001 from toggling at this time. In response to a change in the value of latch 1000, LSB decoder 1
The line PMX1 from 10 goes high and the line PMX0 from there returns to low. Therefore, multiplexer 124 selects the second of the four bits stored in latch 112 (designated BIT1) for output to serial input/output terminal SDn.

Upon the next low-to-high transition of the serial clock signal at terminal SCLK, latches 1000 and 10
The content of 01 becomes the value 10. Therefore, LSB decoder 10 drives line PMX2 high and returns line PMX1 to its low state. The low to high transition on line PMX2 causes a low to high transition at the output of OR gate 120 and resets the output of RS latch 118 to a low level (as shown in FIG. 3). The contents of the latch 112 are output on the third and fourth serial input/output terminals SDn.
Since no data is lost by the separation of data register 8 from latch 112, this separation allows a new set of four bits to be selected in data register 8 without splitting the contents of latch 112. It becomes possible to do so. The third bit stored in latch 112 (ie, BIT2 in FIG. 3) is selected for output by multiplexer 124 in response to line PMX2. Latch 1 is activated by the next period of the serial clock signal of terminal SCLK.
The contents of 000 and 1001 will be increased to the value 11, and the LSB decoder will subsequently assert line PMX3 and pull line PMX2 low. Therefore, the output of NAND gate 104 goes from high level to low level. Line SI controls multiplexer 102 to connect NAND gate 10 for the T and T inputs of latch 1002.
4 output, the T input of latch 1002 will undergo a transition from low to high and change state (
(See line T INPUT 1002 in FIG. 3)
. By toggling the latch 1002, the latch 100
The values stored in 2 through 1007 are incremented and the pre-decoder 8 and serial decoder 10 select the next group of 4 bits of the data register 8 in response. However, since the output of RS latch 118 is low, data register 8 is isolated from latch 112, and therefore the selection of the next group of 4 bits causes the data stored in latch 112 to be output at serial input/output terminal SDn. Don't interfere. The fourth bit of latch 112 is shown in FIG.
is selected for output power by multiplexer 124 responsive to line PMX3 being high as shown at 3. This fourth
The th bit is of course from the previous set of four bits of the data register selected by the serial decoder 10.

The next low-to-high transition of the serial clock signal at terminal SCLK causes latches 1000 and 100
Increase the contents of 1 to the value 00. As previously discussed, this sets the output of RS latch 118 such that pass transistor 116 communicates the four selected bits of data register 8 to latch 112 for output therefrom. The line PMX0 is asserted above and the BI of FIG.
The first of the four bits of latch 112 is selected for the output designated T0'.

From the above discussion, it is clear that the serial output of data from dual port memory 1 does not require decoding the entire contents of counter 22 for each incrementing position of data register 8. It is clear that this occurs without any problems. The only operation required for the second through fourth bits stored in latch 112 is to decode the two least significant bits stored in latches 1000 and 1001 and to decode the other data bits in latch 112 by multiplexer 124. All you have to do is select.

Line T INPUT 1002 in FIG.
, where the dotted line indicates the time the T input to latch 1002 is toggled without a pipeline mechanism. The Q and Q_ outputs of latch 1001 connected to the T_ and T inputs of latch 1002 cause the remaining latches 10
0n, the latch 1002 has its maximum value 11
latch increasing from 1000 to its overflow value 00
and toggle the contents of 1001. Thus, the second
The pipeline mechanism of the circuit shown allows the most significant bit of the data register address to be decoded one serial clock period earlier in time, thus (in the previous example) the next set of 4 bits. By the time the first bit is output, the value stored by the five most significant bits of counter 22 has been incremented and becomes decoded. This structure therefore provides a faster serial output stream than conventional serial ports, which require decoding the contents of counter 22 after each serial clock period increment.

However, the initial increment of the six most significant bits of counter 22 presents a problem if a serial input is desired. For example, the contents of latch 1002 are
If toggled while being serially input to the 4th bit of 4 in the previous group (line PMX3 is high),
The contents of the four bits stored in latch 112 are stored in an incorrect location in data register 8 (ie, the four bits one group before the originally selected group). Therefore, pipelines should preferably be disabled for serial input. To accomplish this, rather than connecting the true and complement outputs of NAND gate 104 to the T_ and T inputs of latch 1002 by line SI, the Q and Q_
This is achieved by selecting the output. In this way,
In the case of a serial input, the signal seen at the T input of latch 1002 will be as shown by the dashed line in FIG. The contents of 1007 to 1007 are incremented and decoded. This ensures that the serial input data received at serial input/output terminal SDn via latch 112 is written to the desired location of data register 8.

The address of the new starting position of data register 8 is sent to latch 1000 via lines PS0 to PS7.
1007 through 1007 respectively, an incorrect addressing occurs if the new address contains the value 11 in the two least significant bits. Such a problem occurs when latch 100 toggles the contents of latch 1002 immediately after the state of line PS2 is latched into latch 1002.
This can be caused by line PMX3 generated by LSB decoder 110 in response to the value 11 of 0 and 1001. For example, the preferred address value is 0000 00112
, the address value decoded by pre-decoder 108 and serial decoder 110 will be 0000 01112 due to the undesired toggling of latch 1002.
, 4 bits before the preferred location of data register 8. Therefore, the initial decoding of the first group of four bits is preferably performed according to the actual value of the address without the value 11 of the two most significant bits "preempting" the next group of four bits.

The circuit of FIG. 2 causes latch 1 to load until the first group of four bits is loaded into latch 112 for output
This provides the possibility of loading a new address into the counter 22 while avoiding an undesirable increment of the six most significant bits stored in 002 to 1007. A high logic level on line LDEN allows latch 100n to be loaded with a logic state on lines PS0-PS7. This high logic level is passed through inverter 111 to the input of NAND gate 104, so that N
The output of AND gate 104 is prevented from toggling regardless of the state of line PMX3. A high logic state on this line LDEN turns on pass transistor 114,
Therefore, the four bits corresponding to the values stored in latches 1002-1007 are conveyed to latch 112 immediately after decoding. As previously mentioned, the output of LSB decoder 110 controls multiplexer 124 to output serial input/output terminal SDn.
One of the four bits of latch 112 for output at
Select bits.

Once line LDEN returns low, pass transistor 114 is turned off and line PMX3
state again toggles latch 1002 and latch 11
Change the selected state of the fourth bit of 2. Because of this toggle, pre-decoder 108 and serial decoder 10 select the next group of four bits for output while outputting the fourth bit from the previous group, as described above. become. As mentioned above, the line PMX
A high logic state on 2 resets RS latch 118, so latch 1 remains on while the next group of 4 bits is selected.
12 is separated from data register 8. AND gate 122 and OR gate 120 are provided to indicate that latch 112 is 11 when the two least significant bits of the loaded address are 11 (i.e., there is no PMX2 signal to reset RS latch 118). to be separated. If line LDEN and line PMX3 are both in a high logic state at the same time. (i.e. the loaded address is 11
), the AND gate 122 causes a high level to appear at the OR gate 120, thus causing the RS latch 118 to
is reset and pass transistor 116 turns.
It will be turned off. Line LDEN turns on pass transistor 114 and disables the toggling of NAND gate 104 so that the 4 selected by the new initial address
The bit is transferred to latch 11 via pass transistor 114.
2 and the 4th bit is loaded into LSB decoder 1
selected by multiplexer 124 in response to a high logic state on line PMX3 from zero.

If line LDEN subsequently returns to a low logic state while line PMX3 is high, pass transistor 114
turns off, OR gate 120 and AND gate 1
Since the latch 118 is reset by the operation of 22,
A latch 112 is isolated from data register 8. Similarly, when line LDEN subsequently returns to a low logic level (line P
The output of NAND gate 104 goes low (although MX3 is high), toggling the T output of latch 1002 and incrementing the count stored in latches 1002-1007. This causes predecoder 8 and serial decoder 10 to decode the incremented count and data register 8
The next corresponding group of 4 bits can be selected. As previously mentioned, on the next period of the serial clock signal at terminal SCLK, line PMX0 is connected to latches 1000 and 1001.
toggles high, setting RS latch 118 and connecting the four selected data bits of data register 8 to latch 112 for output therefrom.

Referring now to FIG. 4, another preferred embodiment of the present invention will be described. The elements of the embodiment shown in FIG. 4 perform functions like the elements of the embodiment of FIG. 2 and are designated by the same reference numerals. The embodiment of FIG. 4 performs pipelining depending on the state of the least significant bit of the address stored in latch 1000. Therefore, latches 1001 to 1
The seven most significant bits of the address stored in 007 are decoded by predecoder 108 and serial decoder 10 to select 2 bits of the 256 bits of data register 8.

Multiplexer 102 in serial output mode connects Q and Q_outputs of latch 1000 to latch 1001.
respectively to the T and T_ inputs of latch 1
In response to the content of 000 switching from 0 to 1,
Latch 1001 one period before the serial clock signal of the execution value.
toggle. This allows predecoder 108 and serial decoder 10 to increment the contents of the seven most significant bits of the stored address while outputting the second of the two bits of the previous group. Ru. In series input mode, multiplexer 102 allows latch 10
Reverse the connection between 00 and 1001 and latch 1
The Q and Q_ outputs of 000 are connected to the T_ and T inputs of latch 1001, respectively, similar to the connections of the other latches 1001 to 1007. Thus, the signal on line SI controls multiplexer 102 for selection of pipeline connections in serial output mode. Similarly, the Q
The series input mode connection of the
Selected while loading latches 1001-1007 from S7. Latch 112 is 2-(two)1
(2 to 1) multiplexer 124 whose control input is connected to latch 1000.
to select between two bits of information stored therein for conveying to the serial input/output terminal SDn.

Pass transistor 114 is connected between data register 8 and latch 112 to transmit two bits of data therebetween. Only one pass transistor 114 is shown in FIG. 4 for clarity as in FIG. 2, but of course two pass transistors 114 are used for each of the two data lines and the tristate Buffers are also used in that location. The gate of pass transistor 114 is connected to the output of OR gate 200. OR gate 200 has three inputs, one of which is connected to the output of AND gate 202, and the other two inputs are connected to lines LDEN and SI. In this way, pass transistor 114 (line L
DEN is at a high logic level) latches 1001 to 1
Becomes conductive in series input mode (line SI is at a high logic level) during loading of 007 or during times when the serial clock signal on line SCLK and the Q_output of latch 1000 are both high. .

The operation of the alternative preferred embodiment of FIG. 4 will now be described with reference to FIG. 5, which is shown after loading of latches 1000-1007 during serial output mode. The Q output of latch 1000 is shown as changing the full period of the serial clock signal received on line SCLK. Since we have selected serial output mode, latch 1001
The T input of latch 1000 follows the Q output of latch 1000, and the contents of latches 1001-1007 increase in response to the Q output of latch 1000 making a low-to-high transition. The dashed waveform of the T input of latch 1001 shown in FIG.
_ Shows the relationship between outputs. Therefore, in serial output mode, the contents of latches 1001 through 1007 increase one full period of the serial clock signal earlier than when they increase in serial input mode (i.e., without the pipeline mechanism described herein). To increase.

In the serial output stream, lines SI and LDE
Since N are both low, OR gate 200 is responsive to the output of AND gate 202. AND gate 202 is connected when the Q_output of latch 1000 is high (and therefore Q1 in FIG.
000 is low) and has a high output when the serial clock signal on line SCLK is high. OR gate 20
A high output from 0 turns on pass transistor 114 and connects the selected pair of bits from data register 8 to latch 112. After the serial clock signal on line SCLK returns low, pass transistor 114 is turned off and latch 112 is connected to data register 8.
separated from As mentioned above, since the T input of latch 1001 makes a low-to-high transition such that the Q output of latch 1000 is high, the seven most significant bits of counter 22 are incremented and the 7 most significant bits of counter 22 are incremented and It is decoded by a serial decoder 10. This is the second bit of the previously selected pair (e.g. BIT
This occurs when 1) appears at the output. Since the output of OR gate 200 is low at this time, pass transistor 114 isolates latch 112 from data register 8 so that the output data is connected to latch 100.
1 to 1007 is not disturbed by the completion of the decoding of the incremented contents of Terminal SC
occurs during this period of the LK serial clock signal. Terminal S
In response to the next low-to-high transition of the CLK serial clock signal, the output of OR gate 200 will go high, thus increasing the pass signal.
Transistor 114 transfers the next group of two bits selected in data register 8 to latch 112, and the Q_output of latch 1000 directs the first of the two bits for output via multiplexer 124. This is indicated by BIT0' in FIG.

During serial input, as in the embodiment of FIG. 2, pipelined decoding is preferably disabled in this example so that the second bit of the input data is written two bits before the desired position. It is better to avoid it. Therefore, line SI causes multiplexer 102 to route the Q and Q outputs of latch 1000 to the T outputs of latch 1001.
_ and T input, respectively, and connect the other latch 100n
Let them do the same thing. Furthermore, since this decoding occurs consistently with the input data, line SI, via OR gate 200, leaves pass transistor 114 conductive throughout the series input operation.

Similar to the embodiment of FIG. 2, the structure of FIG. can. During this loading, if line LDEN is at a high logic level, multiplexer 102 connects the Q and Q_ outputs of latch 1000 to the T_ and T inputs of latch 1001, respectively, and so on to other latches 100n. In this way,
An initial increase in the state of 1001 indicates that data register 8
will no longer disturb the first output bit from the . Furthermore,
OR gate 200 turns on pass transistor 114 in response to line LDEN being high, so that the bit pair selected by the new contents of counter 22 is passed serially to latch 112. Once line LDEN returns low, operation continues as described above with respect to FIG.

It should be noted that the features of the embodiments described herein can, of course, be applied to various structures on the serial side of the dual-port memory 1, such as the split data register 8. These split data registers 8 allow transfers between a split data register 8 and one of the transfer gates 4 to be transferred from another split data register 8, such as an output using the pipelining disclosed herein. during serial output.

Although the present invention has been described above with reference to embodiments, it should be understood that this description is merely an example and is not intended to be construed as restrictive. Furthermore, it is to be understood that many changes to the details of and additions to these embodiments of the invention will be apparent and possible to those skilled in the art upon reference to this description. Additionally, those skilled in the art will be able to use current and future equivalent configurations to achieve the same results as the described embodiments.
Those described here may be easily substituted. All such modifications, substitutions, and additional embodiments are intended to be within the spirit and scope of the following claims.

[0051] In connection with the above description, the following sections are further disclosed.

(1) having an array of memory locations arranged in rows and columns and a register, the register being responsive to a serial clock signal to store the contents of a plurality of memory cells in a selected row of said array; in a type of memory that can transfer data from its registers and output the data serially at a serial output terminal.
a counter arranged in a most significant portion and a least significant portion to store a value corresponding to a position in the register, the counter receiving the serial clock signal; a decoder connected to said counter and said register to select a plurality of positions in said register according to a value stored by said top portion of said counter; a latch for storing the contents of a plurality of register locations selected by the register; means connected between the register and the latch for selectively isolating the latch from the register in response to an isolation control signal; connected to said lowest portion of the counter for generating said separation control signal to said separation means in response to the contents of said lowest portion of said counter and stored by a predetermined set of stages of said counter; and control logic that increases the content of the serial control circuit.

(2) In the series control circuit described in item (1), the counter is a ripple controller including a plurality of stages.
a counter, each of said stages having a toggle input, a bottom stage of said counter receiving said serial clock signal at its toggle input, and a bottom stage of said top portion of said counter having a toggle input; a series control circuit having a toggle input connected to the output of the next lowest stage; and each other said stage having a toggle input connected to the output of the next lowest stage.

(3) In the series control circuit according to paragraph (2), the control logic is configured to control the control logic in response to the lowest portion of the counter having a value less than an overflow. A series control circuit that provides a toggle input to the lowest stage of said top portion of the counter.

(4) In the series control circuit as described in paragraph (2), the stages of the counter further have a preset input and a loadable input, so that each stage responds to the loadable signal to Series control circuit loaded with logic states of preset inputs.

(5) In the serial control circuit according to item (4), the separating means connects the register to the latch in response to the load enable signal.

(6) In the series control circuit according to paragraph (5), the control logic is configured to control the most significant portion of the counter in response to the least significant portion of the counter reaching its maximum value. Series control circuit to increase.

(7) In the serial control circuit according to paragraph (6), the control logic is configured to operate in response to the load enable signal as the lowest portion of the counter reaches the maximum value. A series control circuit in which the contents of said predetermined set of stages cannot be increased.

(8) The series control circuit described in paragraph (1), further comprising: a serial control circuit connected between the latch and the serial output terminal, and responsive to the contents of the lowest portion of the counter; a serial multiplexer having a control input for selecting a position of one of the latches for communication of data with the serial output terminal;

(9) The serial control circuit according to item (1), wherein the least significant portion of the counter stores a single bit.

(10) In the serial control circuit described in item (1), the first stage of the counter stores a plurality of bits.

(11) In the serial control circuit according to paragraph (1), the control logic is configured to control the most significant portion of the counter in response to the least significant portion of the counter reaching its maximum value. Series control circuit to increase.

(12) The serial control circuit of paragraph (11), wherein the control logic generates the separate control signal prior to incrementing the contents of the predetermined set of stages.

(13) an array of memory locations arranged in rows and columns, and means connected to the array for selecting a row of the memory locations in response to a row address signal;
a serial access terminal and a register including a plurality of locations, the serial access terminal being connected between the array and the register to transfer the contents of a plurality of memory cells in a selected row of the array to the register; means, a serial clock terminal for receiving a serial clock signal, and a counter comprising a number of stages and storing a value corresponding to a position of said register, the lowest stage of said counter being connected to said serial clock terminal. operatively connected to a predetermined set of stages of the counter, the contents thereof being incremented in response to the serial clock signal; a decoder for selecting a plurality of positions of said register in response to contents, said predetermined set of stages representing the most significant bits of said counter; a multiplexer for communicating the contents of a selected one of the plurality of register locations therebetween, the selected register location corresponding to the remaining contents of the counter and not in the predetermined set of stages; and being connected to the remainder of the counter to increase the contents of the predetermined set of stages of the counter in response to the remainder contents of the counter reaching a predetermined value other than its overflow value. memory containing control logic;

(14) The memory according to item (13), further comprising an isolation device connected between the register and the latch to isolate the latch from the register in response to a isolation control signal. means and said control signal also generating said isolation control signal in response to said remaining contents of said counter reaching a predetermined value other than its overflow value.

(15) The memory according to paragraph (13), wherein the remainder of the counters includes a single stage. (16) In the memory described in paragraph (13),
A memory in which the remainder of the counter includes multiple stages.

(17) In the memory described in paragraph (13), the counter is a ripple counter, the stage thereof has a toggle input, and the lowest stage of the counter has a toggle input of the toggle input. wherein the serial clock signal is received, the toggle input of the lowest stage of the predetermined set is connected to the control logic, and the toggle input of the other stage of the counter is connected to the output of the next lowest stage. And,
the control logic, in response to the remaining contents of the counter reaching a predetermined value other than its overflow value;
providing a signal to the toggle input of the lowest stage of the predetermined set.

(18) In the memory of paragraph (17), the control logic is responsive to a serial selection signal indicating a serial input mode in which the register is to receive serial input data; The control logic of the memory increases the contents of the predetermined set of stages in response to the remaining contents reaching an overflow value.

(19) A memory according to paragraph (18), wherein the memory is for the serial access terminal to likewise receive serial input data.

(20) In the memory described in item (19), the control logic is an LSB decoder connected to the output of the remaining stage of the counter, and the decoder is connected to the output of the remaining stage of the counter. a control multiplexer having an output corresponding to a predetermined value other than its stored overflow value; and a control multiplexer having a data input connected to the output of the LSB decoder and an output of the topmost stage of the remaining stages. a control input for receiving the serial input selection signal, and an output connected to the toggle input of the least significant bit in the predetermined set, thereby an output of the top stage of stages is communicated to an output of the control multiplexer during the serial input mode, and an output of the LSB decoder is communicated to the output of the control multiplexer when not in the serial input mode. memory.

(21) The memory according to paragraph (19), wherein the remainder of the counters includes a single stage.

(22) In the memory described in item (21), the control logic is a control multiplexer, and has a data input connected to the output of the remaining stage;
a data input connected to the complement of the output of the remaining stage;
an output connected to a toggle input of the least significant bit in the predetermined set and a control input receiving the serial input selection signal, such that the output of the multiplexer is connected to the toggle input of the least significant bit in the predetermined set; provides a toggle signal to the least significant bit in the predetermined set during the serial input mode in response to the contents of the output of the control multiplexer and the output of the remaining stages when not in the serial input mode. and giving it a toggle signal in response to the memory changing but not overflowing.

(23) Discloses a dual-port memory featuring pipelined serial ports. The serial side of the dual-port memory includes a ripple counter 22 divided between predetermined stages. The contents of the stages above the dividing point are decoded and output to 1 of serial register 8.
Selects the bits of the group and its contents are latch 11
Latch at 2. In a serial output, the contents of the stages below the break are decoded, so that in response to the stages below the break reaching a certain value, the stages above the break are incremented, and the incremented value is decoded. be done. Pass transistor 1 between resistor 8 and latch
14, 116 are turned off during such times that the increased value is being decoded, so the new value does not disturb the output. The latched outputs are selectively represented by multiplexer 124, which selects the latched bits in response to the values of the stages below the split. When the value of a stage reaches its maximum value (i.e., the first bit of the next group), pass transistors 114 and 116 are enabled to output the contents corresponding to the increased contents of the stages above the divide. Let it be expressed as follows. Logic is provided to prevent stage separation during serial input and to prevent initial increment of counter 22 prior to storage of input data. Logic is similarly provided so that after the counter is loaded with a new value, the first bit is output first, unencumbered by the initial increments of the counter stages above the divide.

[Brief explanation of the drawing]

[Fig. 1] Dual port configured according to the present invention.
1 is a schematic block diagram of a preferred embodiment of a memory.

FIG. 2 is a schematic electrical diagram of a first embodiment of the serial input/output circuit of the memory of FIG. 1;

FIG. 3 is a timing diagram illustrating the operation of the serial output from the circuit of FIG. 2;

FIG. 4 is a schematic electrical diagram of a second embodiment of the serial input/output circuit of the memory of FIG. 1;

FIG. 5 is a timing diagram illustrating the operation of serial output from the circuit of FIG. 4;

[Explanation of main symbols]

1 Dual port memory 8 Data register 10 Serial decoder 22 Counter 100n, 112 latch 102, 124 Multiplexer 108 Pre-decoder 110 LSB decoder

Claims (2)

[Claims] 1. A memory comprising a plurality of cells arranged in rows and columns and storing binary data in the plurality of cell positions, the memory comprising: a register capable of transferring contents of the plurality of cell positions in the row; and a register capable of transferring the contents of the plurality of cell positions in the row; selection means for sequentially selecting a group of register locations for outputting data in groups; a latch connected to receive a group of data from the group of register locations selected by the selection means; and a latch connected to receive a group of data from the group of register locations selected by the selection means; an intermediate data line for transferring the data group to the latches; a multiplexer for serially outputting the data stored in the latches; and a multiplexer for serially outputting the data stored in the latches; circuitry for isolating a next group of data from the latch so that it is not transferred to the latch via the intermediate data line. 2. Claim 1, wherein the selection means controls a multiplexer for serial transfer of data stored in the latch.
Memory listed.