JPS60170087A - Parallel readable memory - Google Patents

Abstract

PURPOSE:To obtain a memory capable of reading out in parallel by taking out plural data lines in correspondence to respective address from one memory, and reading circuits in correspondence to respective processors, and selecting only signals on one data line. CONSTITUTION:A bit slice control circuit 2 sends slice signals from right to left (or from left to right) sequentially to a signal line 3, and outputs contents of the bit concerned of all words of a memory array to a data line 4 in parallel. On the other hand, K-number of processors to read out memory give necessary addresses to an address decoder 6 through an address line 5. Each address decoder decodes addresses independently and outputs the prescribed word address. At this time, these processors give to a mask register 7 information in an accress vector (0, 0, ..., 1, ..., 0) to assign ''1'' to the position in correspondence to the desired word number to be outputted out of N-number words and ''0'' to the others. Since a data vector (m1j, m2j, ..., mnj) is inputted to the mask register 7 through the data line 4, the word is masked by the address vector and only the contents of word data of ''1'' are selected and outputted to an output data line 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a memory that can be read simultaneously by a plurality of processors.

[Background of the invention]

Conventional memory has a single address input single data (input/output) configuration, and has the characteristic that it can only be accessed by one processor at a time.

Although this characteristic is advantageous in the sense of avoiding confusion during memory writing, it is disadvantageous in that it limits parallel processing when reading without such concern.

[Purpose of the invention]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a parallel readable memory structure.

[Summary of the invention]

In order to achieve all of these objectives, we will describe the structure of parallel IJ readout without trenches, and derive the present invention from there.
! ! - Consider the case where multiple people read the data.

Physically, there is only one piece of data on paper, and there is no duplication. However, the light emitted from the light source is diffusely reflected on the paper and reaches each person's eyeball through multiple paths. In this process, data exists redundantly on each path. Each person selects the necessary part of all the data reaching their eyeballs. This choice is not influenced by the choices of others. In other words, it is considered basic that one stored data is broadcast over multiple communication channels and selected independently.

In Bokuchomei, the above data lines are taken out from one memory for each address, and are guided to the readout circuit section corresponding to each processor to select only the signal on one data line. The basic structure has been realized. In order to reduce the cost of the communication path, the two data are arranged in a 4t'l configuration in which the bit slice method is used.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. Memory array 1 can store N words by purchasing n bits per word. The bit slice control circuit 2 sequentially sends slice signals from left to right (crosswise or right to left) onto the signal line 3, and outputs the contents of the corresponding bits of all words of the memory array onto the data line 4 in parallel. That is, if the contents of the ``th'' bit of the first word are denoted by m l j , then when the slice signal that excites the jth bit is input, the data line 4 receives ml j ,
lTl2 j .

m3j..., mHl are output simultaneously.

On the other hand, a single processor for reading memory supplies a necessary address to an address decoder 6 via an address line 5. Each address decoder decodes each other independently and outputs two specific word addresses. At this time・N(
Address vector (
0, O, . . . , 1° . . . , 0). Mask register 71C1,j
Data line 4 provides data pect /l/ (rTlt j
, rr12j, .

Since the bit number being sliced is output from the bit slice control circuit 2 to the signal line 9, the processor side can read the memory at any timing. Further, by specifying and outputting an arbitrary pit width among the n bits using the signal line 10, the word length can be changed or the data content can be restricted.

Writing to memory is done using a write-only decoder 111C.
This is done by giving an area address to the address line 12 and data to the data line 13. The timing of providing data shall be controlled on the write side using the slice bit number on the signal line 9.Next, the structure of the memory cell will be explained using Figure 2.@The cell is called an RS flip-flop. Although it is mainly composed of circuits, it may be of any type as long as it is functionally equivalent. The difference from normal memory cells is that a bit slice signal line is required.

(1) Write 1 write signal W (IJ and O write signals W(0) are given by data lines 21 and 22, respectively, word address signal is given by address line 23, and bit slice signal is given by signal #!24. The inputs S and R of the flip-flop 25 are determined.W(1)=1°W(0)-0 selects the word address (address signal -11 and bit slice signal; if 1, S=O, Since 几=1, 1 is set in the flip-flop 25. Conversely, if W(1)=0, W(0)mi1, and other things being the same, 0 is set.

(2) When O is applied to the read address line 23, 5=iL=1 and Q
The IC outputs the contents stored in the flip-flop. When the bit slice signal is -0, this value is always output as 1 to the data line 26 by the NAND gate, but when the bit slice signal is -1, if the content is 1, it will be O, and if the content is O, it will be 1. Output. Since a wired OR is established on the data line 26, the data content can be determined by knowing the value mi.

Q=O.

In the above explanation, writing is also performed by bit slicing, but simultaneous writing can be performed by removing the bit slicing signal from the input to the S of the memory cell and the input NAND gate.

〔Effect of the invention〕

According to the present invention, one memory can be read by a plurality of processors at the same time, which has the effect of increasing the degree of freedom in configuring n parallel processors. Reading requires n+-1 cycles including address decoding. Assuming that a normal memory can be read in two cycles, 1. In order for the memory of the present invention to be faster than a normal memory IJ i, the relationship between the number of processors N and the word length n must not satisfy 2N>n+1. Must not be. When n=16, N is 9 or more, and when n=32, it is fl"!NI'!17 or more. However, when simultaneous access requests are issued to normal memory, no control is performed to avoid conflicts. Considering that two more cycles are required for this, the above equation becomes 4N>n+1.

When n=16.32, N=5.9, respectively.5 Also, this method has the advantage that a contention avoidance control circuit is not required.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of a parallel readable memory. FIG. 2 is a structural diagram of a memory cell. 1...Memory array, 2...Bit slice control circuit. 3... Signal line, 4... Data line, 5... Address line, 6... Address decoder, 7... Mask register, 8... Output data line -9, 10... Signal line, 1
1...-M included dedicated decoder 12...Address line, 13...Data line, 21.22...Data line, 2
3...Address line, 24...Signal line, 25...Flip-flop, 26...1st day 2nd day

Claims (1)

[Claims] 1. A memory with a bit slice control circuit that can read out the contents of a memory with an n-bit word structure sequentially from the end in parallel for all words 1/CI bit at a time, and an address decoder that specifies a specific word address and outputs only that data. A parallel readable memory comprising a plurality of Jc extraction circuits that mask data at other addresses.