JP2002544586A - Apparatus and method for a programmable data path arithmetic array - Google Patents

Abstract

(57) [Summary] To solve the problem that as the device architecture becomes more generalized, the structured data path function suffers more inefficiency and performance degradation. Provide a programmable architecture with improved function performance and device usage efficiency. A programmable data arithmetic array (300) includes a series of data buses (320), a data arithmetic unit including a fixed function unit (312) and a programmable function unit (314) connected to the series of data buses. And a matrix of A bidirectional interconnect is located between the series of data buses and the data arithmetic unit.

Description

DETAILED DESCRIPTION OF THE INVENTION

(Description of Related Application) [0001] This application is related to US Provisional Patent Application No. 60-133,134 filed on May 7, 1999.
Claim priority over the issue. TECHNICAL FIELD The present invention relates generally to logic circuits used to perform computer intensive tasks, and more particularly, to computer intensive tasks such as wireless communications. The present invention relates to a useful hybrid logic circuit.

BACKGROUND ART In the electronics industry, programmable logic devices are widely used. Conventional programmable logic devices typically include a general purpose logic array and a general purpose interconnect. A typical logic array in a general purpose field programmable gate array (FPGA) is designed to support certain random / control logic functions and certain structured / data path logic functions. If the program logic functions include many data path functions, the use of FPGAs can be very inefficient. If generalized random / control logic and routing resources are used for structured data path functions, it will result in inefficient device usage and performance degradation. The more generalized the device architecture, the more inefficiency and performance degradation will be incurred by the structured data path function. Therefore, there is a need to provide a programmable architecture with improved performance of structured data path functions and improved device utilization.

DISCLOSURE OF THE INVENTION A programmable data path arithmetic array includes resources that are data buses connected to a matrix of data arithmetic units that include fixed functional units and programmable functional units. In an exemplary embodiment, the programmable data path arithmetic array includes only fixed functional units. In another exemplary embodiment, the programmable data path arithmetic array includes only programmable functional units. A bi-directional interconnect is provided between the data bus and the matrix of data arithmetic units to facilitate dynamic reconfiguration and the feasibility of a programmable data path arithmetic array.

[0004] Unlike FPGAs, a programmable datapath arithmetic array includes two organized logical resources: a datapath slice and a datapath structure. In an exemplary embodiment, the programmable data path arithmetic array includes a data path slice array. For example, if the programmable data path arithmetic array is a 1 × N array, N represents the number of data path slices. The datapath slice includes a datapath structure array. In the exemplary embodiment, the data path slice is 1x
If it is an array of M, M represents the number of data path structures. The data path structure includes a bit slice block array. In an exemplary embodiment, if the data path structure is a 1 × L array, L represents the number of bit slice blocks. The bit slice block contains the building blocks of the programmable data path arithmetic array. The bit slice block includes a bit unique unit and a common control unit. In the exemplary embodiment, the programmable data path arithmetic array includes two types of data path structures, a fixed data path structure and a re-programmable data path structure. The fixed data path structure performs a limited set of functions, while the reprogrammable data path structure performs a relatively large set of functions.

[0005] Programmable data path arithmetic arrays include dedicated routing resources. Further, in a preferred embodiment, the programmable datapath arithmetic array includes coarse-grained logic. In an exemplary embodiment, the programmable data path arithmetic array is designed to facilitate and accelerate data path functions. Examples of data path functions include counters, incrementers, decrementers, shifters, scalers, adders, subtractors, accumulators, and decumulators. In the exemplary embodiment, the data path function indicates structural uniformity across all bits.

FIG. 1 shows a prior art field programmable gate array (FPGA) 100 implemented to provide a data path function. The FPGA 100 includes a bus connection function assembled from general resources. Each bus bit is
It is formed by non-deterministically connecting the three-state driver 102 and the programmable interconnect point 104. More specifically, each three-state driver 102
Has an associated resource array 110. Each resource array 110 includes a programmable interconnect point 104, and these programmable interconnect points 10
4, a signal line 112 is provided. As shown in FIG. 1, the bus connection function is implemented by using a programmable interconnect point 104 and
It is programmed randomly in the PGA 100.

FIG. 2 illustrates a programmable data path arithmetic array 120 according to one embodiment of the present invention. Array 120 comprises a matrix of data path units 122. Each data path unit 122 may be a fixed function unit,
It may be a re-programmable functional unit. Reprogrammable functional units can include, for example, general programmable logic blocks such as field programmable gate arrays. In addition, the reprogrammable functional unit
It has fine granularity and internal connectivity for dynamic configuration of functionality. The fixed function unit is
It is a unique function block such as a multiplication accumulation circuit, a barrel shifter, a comparator, a parity generator, a masking function circuit, a packing function circuit and an ordering function circuit,
It is not limited to these.

As shown in FIG. 2, a row of data path units 122 form a bus connected data path arithmetic unit 124. Programmable bi-directional interconnect 126 connects each data path unit 122 to resources programmed to be used as data bus 128. Preferably, the data path arithmetic unit interconnect 130 is also used to connect to an adjacent data path arithmetic unit 122. The programmable data path arithmetic array 120 supports computer-based execution of intensive algorithms.

FIG. 3A illustrates an exemplary programmable data path arithmetic array 300 according to one embodiment of the present invention. The programmable data path arithmetic array includes a series of data path slices 302A, 302B, 302C, 302D. Each datapath slice 302 includes a series of datapath structures 304. Each data path structure 304 includes a series of bit slice blocks 306. Each bit slice includes a bit-specific sub-block 308 and a common control sub-block 310.

FIG. 3B illustrates an exemplary programmable data path arithmetic array 300 according to one embodiment of the present invention. The programmable data path arithmetic array 300 includes a plurality of fixed function units 312 and a plurality of re-programmable function units 314. Each unit of fixed function unit or reprogrammable function unit
It is connected to a dedicated tri-state driver 316, a dedicated control interconnection point 318, and a dedicated bus segment 320. That is, the programmable data path arithmetic array logic and routing resources are divided into n-bit groups.

The fixed function unit 312 may include a programmable interconnect and control width and depth attributes. The fixed function units 312 may perform the same or similar functions as one another. Further, the fixed functional unit 312 may be functionally fixed but programmable with respect to width and / or depth. Programmable extensibility of fixed function units can be achieved within fixed function units 312 or by connecting fixed function units 312 together. The present invention provides the fixed function unit 312 and the re-programmable function unit 314 as a single device. The common data path is used by both the fixed function unit and the reprogrammable function unit.

FIG. 4 illustrates an exemplary bit slice block 30 according to one embodiment of the present invention.
6 is shown. Each bit slice block 306 includes a bit-specific sub-block 3
08 and a common control sub-block 310. Each bit-specific sub-block 308 in the bit slice block 306 is
Is unique when compared to each bit-specific sub-block within. Bit-specific sub-block 308 receives input from a corresponding adjacent one or more data bus bits in data path structure 304. For example, for bit slice i, the bit-specific sub-block 308 includes D _i , D _{i + 1} , D _i−1 , bit outputs Q _{i + 1} , Q _i−1 ,
And receive a bus input from the preceding stage of the carry-in (carry-in) C _i. In addition, the least significant bits of the bit-specific sub-block 308 include cascading logic to enable the concatenation (extension) of vertically adjacent data path structures 304.

The common control sub-block 310 of the bit slice 306 includes the data path structure 30
4 includes components common to all common control sub-blocks 310 in all other four bit slices 306. Furthermore, all common control sub-block components in the data path structure are driven by a common control input. For the re-programmable data path structure 304, the control inputs for the common control sub-block 310 are:
Determined by the functions programmed in data path structure 304.

FIG. 4 illustrates an exemplary interconnect relationship between three bit slices 306 A, 306 B, 306 C. The bit slices 306A, 306B, 306C constitute the data path structure 304. A central bit slice 306B having a data bus input D _i and an output O _i connects adjacent data bus bits D _i−1 , D _{i + 1} and adjacent bit slice outputs Q _i−1 , Q _{i + 1} . receive. The carry chain starts at the C _i-2 node of the bit specific sub-block 308. Carry chain C _i-2 travels upward through bit slice 306C, exits at the top, is supplied to vertically adjacent bit slice 306B, and then to 306A. In the exemplary embodiment, common control lines (ADD, Q / D, U / D, SH, L, CE, R, Q / Y)
Are connected to the bottom bit slice 306C of the common control sub-block 310C, and then to the respective bit slices 306B, 306A of the common control sub-block 310B, 310A.

The data path structure 304 constituting the fixed function includes a fixed function unit 312 (FIG. 3).
B) or FFU. As shown in FIG. 5, the fixed function unit 312
Can perform a small number of functions (ie, 10 or less). The data path structure 304 including the function generator based on the look-up table as shown in FIGS. FF
Although U312 and RFU314 can be controlled by the same control line, RFU314
Is more flexible in providing various functions.

FIG. 5 shows an exemplary fixed function bit slice block 306. The fixed function bit slice block 306 includes a carry sum function generator 502 and various input and control signals (D _{+ 1} , D- ₁ , Qi _{+ 1} , Qi _-1 , ADD, Q / D, U / D, SH
, L, CE, R, K).
4, a flip-flop 518, and another multiplexer 520 responsive to the select signal Q / Y. In the exemplary embodiment shown in FIG. 5, the reset signal R is dominant over all other control signals. That is, the bit slice 306 in FIG.
Are referred to as fixed function bit slices. FIG. 5B illustrates the control signal.

In contrast, in the RFU any control signal can be the dominant signal, thus allowing a wider range of functions. FIG. 6 illustrates a reprogrammable data path structure 30.
4 illustrates an exemplary embodiment of a re-programmable bit slice 306 suitable for 4.
In FIG. 6, bit slice 306 includes carry sum generator 602 and variable n
, An n-bit lookup table (f2) 604, a flip-flop 606, and a multiplexer 608. For example, when n = 13,
The number of possible functions is 2113 or 8192 functions. Control is performed by six general-purpose lines G0-G
5 provided. However, as the functions that can be performed by the bit slice 306 increase, the manufacturing cost of the device also increases. That is, it is desirable to determine the reprogrammable performance according to the specific needs of each case.

FIG. 7 shows an exemplary embodiment of a medium reprogrammable bit slice 306. 7, the bit slice 306 includes a carry sum generator 702, a plurality of multiplexers 704 and 706, an n-bit lookup table (f2) 708 capable of executing any function of a variable n, a flip-flop 710, and a multiplexer 712. And In FIG. 7, an n-bit lookup table 708 is a 10-bit lookup table (n = 10), and the number of possible functions is 2110 or 1024 functions. The n-bit lookup table 708 is controlled by five general-purpose lines G0 to G4.

FIG. 8 illustrates an exemplary embodiment of a minimally re-programmable bit slice 306. In FIG. 8, bit slice 306 is provided for carry sum function generator 8.
02, a multiplexer 804, an n-bit lookup table (f2) 806 capable of executing any function of a variable n, a flip-flop 808, and a multiplexer 8
10 is included. Operand selection (D _i , D _{i ± 1} , Q _i , Q _{i ± 1} , and carry sum function generator 802) is performed by the 7: 1 multiplexer 804, and the n-bit lookup table 806 includes three general lines G0 FIG. 8 shows an economical bit slice because it is a 4-bit lookup table (n = 4) controlled by .about.G2. Although only bit slice blocks having an arithmetic object (ie, a carry-sum function generator) are shown in FIGS. 5 to 8, a storage object such as a random access memory can also be used.

FIG. 9 shows two sets of bit slice blocks 306 in which three bit slices are stacked in the vertical direction. In FIG. 9, each set of bit slice blocks 306 is part of the data path structure 304. Each bit slice block 306 is
It is connected to a dedicated data bus 902 via a three-state bus driver 904. Each tri-state bus driver 904 has an output enable signal (OE) on line 906.
1 or OE2). Each data path structure 304 has its own bus driver output enable signal (OE) that is common to all bus drivers 904 of data path structure 304.

FIG. 10 shows the connection possibilities of the data path structure 304. Generally, vertically adjacent data path slices 302 are connectable and lower data path slice 3
02, all of the data path structures 304 in the vertical direction are directly adjacent to the path slice 3
02 is connected to all data path structures 304. For example, FIG. 10 shows an upper data path slice 302A and a lower data path slice 302B. The data path slices 302A, 302B have a three state driver 1002 and line 1
004 and 1006 are connected to each other by an interconnecting point 1001 which is connected by a wiring connected between them. Lines 1004 and 1006 are connected to the output signal (OE) by programmable interconnection points 1008 and 1010, respectively.

The architecture of the present invention is superior to general reprogrammable logic because the fixed function unit 312 provides dedicated high-speed resources similar to ASIC logic. The present invention is superior to fixed-function ASIC logic because the reprogrammable functional unit 314 provides dynamic and flexible resources similar to FPGAs.

The reprogrammable data according to the present invention, because the logical resources are systematic, the logical resources are fixable and / or reprogrammable, and the routing resources are bitwidth expandable (by n-bit multiplication) Various embodiments of the path arithmetic array have advantages over existing systems. Further, the reprogrammable datapath arithmetic array of the present invention allows for higher performance datapath functions.

The foregoing description, for purposes of explanation, uses specific terms to provide a thorough understanding of the present invention. However, one of ordinary skill in the art will not require particular detail in practicing the present invention. In other instances, well-known circuits and devices have been shown in block diagram form in order not to obscure the nature of the invention. That is, the foregoing description of specific embodiments of the present invention is intended to be illustrative of the present invention. This is exhaustive and is not intended to limit the invention to the precise form disclosed, and obviously, many modifications and variations are possible in light of the above teaching. The embodiments have been selected and described in order to best explain the principles of the invention and its practical applications, so that those skilled in the art will recognize the invention and its various modifications that may be advantageous for a particular application. And various embodiments including The scope of the invention is defined by the claims and their equivalents.

[Brief description of the drawings]

FIG. 1 shows a conventional FPGA implemented to provide a data path function.

FIG. 2 illustrates a programmable data path arithmetic array according to one embodiment of the present invention.

FIG. 3A illustrates a programmable data path arithmetic array according to one embodiment of the present invention.

FIG. 3B illustrates a programmable data path arithmetic array according to one embodiment of the present invention.

FIG. 4 illustrates an exemplary bit slice block according to one embodiment of the present invention.

FIG. 5A illustrates a fixed function bit slice block according to one embodiment of the present invention.

FIG. 5B is a list of control signals according to one embodiment of the present invention.

FIG. 6 illustrates a re-programmable bit slice block according to one embodiment of the present invention.

FIG. 7 illustrates a medium reprogrammable bit slice block according to another embodiment of the present invention.

FIG. 8 illustrates a minimal re-programmable bit slice block according to one embodiment of the present invention.

FIG. 9 illustrates an exemplary programmable data path arithmetic array according to one embodiment of the present invention.

FIG. 10 illustrates another exemplary programmable data path arithmetic array according to one embodiment of the present invention.

[Procedural Amendment] Submission of translation of Article 34 Amendment of the Patent Cooperation Treaty

[Submission date] May 25, 2001 (2001.5.25)

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Claims (8)

[Claims] A series of data buses; a matrix of data arithmetic units connected to the series of data buses; and a bidirectional interconnect disposed between the series of data buses and the data arithmetic units. A programmable data path arithmetic array, including: 2. The programmable data path arithmetic array according to claim 1, wherein said matrix of data arithmetic units includes at least one fixed function unit. 3. The programmable data path arithmetic array according to claim 1, wherein said matrix of data arithmetic units includes at least one programmable functional unit. 4. A resource configured to be used as a series of data buses, wherein each data path group functions as a single data path unit and includes a series of data path objects. A programmable data path arithmetic array comprising: a series of connected data path groups; 5. The programmable data path arithmetic array according to claim 4, wherein said series of data path objects includes at least one fixed function object. 6. The programmable data path arithmetic array according to claim 4, wherein said series of data path objects includes at least one programmable function object. 7. The programmable data path arithmetic array according to claim 4, wherein each data path object in said series of data path objects is configured to perform a predetermined function. 8. The programmable data path arithmetic array according to claim 7, wherein said predetermined functions include a storage function and an arithmetic function.