CN1716210A - Semiconductor devices - Google Patents

Abstract

The invention discloses a semiconductor device, which includes a configuration memory, an arithmetic unit, and a fixed value memory, wherein the configuration memory is used to store configuration data, the fixed value memory is used to store fixed value data to be provided to the arithmetic unit, and the arithmetic The circuit configuration of the cells can be reconfigured according to the configuration data. Since the configuration data and the constant value data to be supplied to the arithmetic unit are stored in different memories, in the configuration memory, it is not necessary to provide a data area for storing the constant value data. Thus, by storing only information for reading out constant value data from the constant value memory, predetermined constant values can be supplied to the arithmetic unit.

Description

Semiconductor device

technical field

The present invention relates to semiconductor devices, and more particularly, the present invention relates to semiconductor devices having a dynamically reconfigurable circuit configuration.

Background technique

Conventional semiconductor devices such as LSIs are generally manufactured by determining the arrangement of AND gates, OR gates, etc., and their interconnection relationship at the design stage in order to perform predetermined processing so that predetermined processing satisfying required specifications can be performed. That is, in order to realize a desired function in a conventional semiconductor device, such a semiconductor device realizing the function is manufactured by designing a circuit configuration (logic configuration) for each gate (at the level of each gate).

Unfortunately, the circuit configuration of the above-mentioned semiconductor device is fixed at the design stage. Therefore, in order to perform processing satisfying different required specifications by changing the specifications or the like, it is necessary to perform the entire design and manufacture each time. This requires a lot of labor and time, and the development cost is also high.

One method of solving this problem is a reconfigurable semiconductor device called a reconfigurable LSI, which can change the processing to be performed by reconfiguring the logic even after manufacture. Such a reconfigurable semiconductor device has a plurality of arithmetic units each receiving a control signal (configuration information) from a CPU and capable of changing its function. These arithmetic units are formed by appropriately combining shifters, ALUs (arithmetic and logic units), selectors, etc., and these arithmetic units can be changed by receiving configuration information from the CPU and reconfiguring the logic accordingly. The processing performed.

Also, as address control regarding the memory, there is disclosed a technique of storing a memory address in a memory (register) (for example, Patent Document 1).

[Patent Document 1]

Japanese Patent Application Laid-open No. Hei 6-309223.

Contents of the invention

An object of the present invention is to reduce the memory capacity required for storing fixed value data in a semiconductor device having a reconfigurable circuit configuration.

A semiconductor device of the present invention includes an arithmetic unit group having a plurality of arithmetic units and having a reconfigurable circuit configuration according to configuration information, a configuration memory, and a constant value memory. The configuration memory stores configuration information to be provided to the arithmetic unit group. The fixed value memory stores fixed values to be supplied to the arithmetic unit group and used for arithmetic processing.

In the present invention, configuration information and fixed values to be provided to the arithmetic unit group are stored in memories that can be controlled independently of each other. Therefore, in the configuration memory, it is only necessary to store information for reading out desired constant values from the constant value memory without forming any constant value data area therein. In addition, the fixed value memory does not need to store a fixed value for each state of the arithmetic processor, ie for each configuration information.

Description of drawings

FIG. 1 is a diagram showing an arrangement example of a reconfigurable semiconductor device;

FIG. 2 is a diagram for explaining contents of a configuration memory shown in FIG. 1;

FIG. 3 is a diagram illustrating an arrangement example of a reconfigurable semiconductor device according to an embodiment of the present invention;

4A and 4B are views for explaining the contents of the configuration memory and the constant value memory shown in FIG. 3;

5 is a diagram showing another arrangement example of a reconfigurable semiconductor device according to an embodiment of the present invention; and

6A to 6C are diagrams for explaining the contents of the configuration memory and the constant value memory shown in FIG. 5 .

Detailed ways

In the aforementioned conventional reconfigurable semiconductor device, since the CPU directly controls a plurality of arithmetic units, the processing speed is low. For example, when the processing to be performed by a plurality of arithmetic units is to be changed based on an interrupt from a certain arithmetic unit, the CPU calls and executes an interrupt handler in response to an interrupt from the arithmetic unit, and then combines the processing with the processing routine Configuration information and the like corresponding to the result are supplied to these arithmetic units. The interrupt processing requires a time equivalent to several tens of clock cycles. Therefore, in the conventional reconfigurable semiconductor device, the processing speed is low, so the processing performed by the arithmetic unit cannot be dynamically changed (for every clock).

As a method to solve this problem, the present application proposes a reconfigurable semiconductor device having an arrangement as shown in FIG. 1 .

FIG. 1 shows a diagram of an example of the arrangement of a reconfigurable semiconductor device proposed by the present applicant. In order to perform change control of the circuit configuration (logic configuration), what this semiconductor device has is not a CPU but a sequencer having a function equivalent to the CPU.

As shown in FIG. 1 , a reconfigurable semiconductor device has a sequencer (controller) 1 and an arithmetic processor 2 .

The sequencer 1 comprehensively controls the semiconductor device according to an instruction from the outside (for example, a processor connected via the external bus 3 ). The sequencer 1 manages and controls to dynamically change the circuit configuration (including logic configuration) of the arithmetic processor 2 . In order to dynamically change the circuit configuration of the arithmetic processor 2 according to the application, the sequencer 1 is connected to the individual functional units of the arithmetic processor 2 via signal lines, so that information including configuration data (configuration information) can be provided from the sequencer 1. control signal.

The sequencer 1 has a state controller 11 , a state register 12 and a configuration memory 13 .

For example, based on a preset sequence or state transition indication signal from the arithmetic processor 2, the state controller 11 generates a configuration memory address for reading configuration data and fixed value data from the configuration memory 13, and also generates a read timing, The configuration data and fixed value data change the state (circuit configuration) of the arithmetic processor 2 to the next state. The generation of the configuration memory address of the state controller 11 is done by reference to information indicating the current state held in the state register 12 . When the current state is changed to the next state, the information held in the state register 12 is updated.

The configuration memory 13 stores configuration data which sets the circuit configuration of the arithmetic processor 2 and setting value data. All configuration data and fixed value data are written into the configuration memory 13 from the outside in advance before the operation starts, and are saved as a pair of data for each state. Under the control of the state controller 11 , the configuration data and fixed value data stored in the configuration memory 13 are read out and output to the arithmetic processor 2 . The contents of the configuration memory 13 will be described in detail later.

The arithmetic processor 2 has a selector/register (bus) 21, an arithmetic unit 22-i, and a data memory 23-j. Note that i and j are suffixes, i is an (arbitrary) natural number from 1 to N, and j is an (arbitrary) natural number from 1 to M.

The selector/register 21 is controlled by configuration data provided by the sequencer 1 . The selector/register 21 is connected to the arithmetic units 22-1 to 22-N and the data memories 23-1 to 23-M, and exchanges data with the arithmetic unit 22-i and the data memory 22-j. In other words, the selector/register 21 has a network function of connecting the arithmetic units 22-1 to 22-N and the data memories 23-1 to 23-M so that the arithmetic units and data memories can communicate with each other.

More specifically, the selector/register 21 supplies data to the arithmetic unit 22-i, supplies write data to the data memory 23-j, and receives read data supplied from the data memory 23-j according to configuration data. Also, the selector/register 21 has a register that temporarily holds, for example, an output from the arithmetic unit 22-i, and can selectively output data held in the register, or data supplied from another location, according to configuration data. (arithmetic result).

Each arithmetic unit 22-i has a register 24 and an ALU unit 27.

The registers 24 include a configuration register 25 and a fixed value register 26 for respectively storing configuration data and fixed value data supplied from the sequencer 1 .

The ALU unit 27 is formed by using, for example, a shift circuit (shifter), an ALU (arithmetic and logic unit), and a selector (for the convenience of description, these components are also simply referred to as an arithmetic unit hereinafter, and there is no need to describe them distinguish between). Note that the ALU unit 27, more specifically, a plurality of (or one) arithmetic units forming the ALU unit 27 may be appropriately selected and determined depending on the application to be used.

In each ALU unit 27 , the operation mode of each arithmetic unit and the connection between the arithmetic units are set based on the configuration data held in the configuration register 25 . That is, according to the configuration data, the circuit configuration of each ALU unit 27 can be changed, and the individual arithmetic units are controlled in such a way that all operations such as addition, multiplication, bit operations, and logic operations (AND, OR, and XOR) can be performed. required function.

For example, the shift amount, the arithmetic shift process, the logic shift process, the masking process of the predetermined bit after the shift process, etc. are controlled in the shift circuit. Also, in an ALU formed by using, for example, an AND (logical multiplication operation) circuit and an OR (logical sum operation) circuit, by appropriately combining these circuits, the circuit (arithmetic) function of the ALU is controlled as a whole. For example, an input to be output among a plurality of inputs is controlled in a selector. In addition, connections between shift circuits, ALUs, selectors, etc. are controlled.

The ALU unit 27 receives the first input data DT1 provided from the selector/register 21 according to configuration data, or the fixed value data CVD stored in the fixed value register 26, and also receives the second Input data DT2. The ALU unit 27 performs a predetermined operation by using these data, and outputs an operation result. Although this output from the ALU unit 27 can be output directly, it can also be fed back based on configuration data. For example, these outputs can be accumulated, normalized, and output.

Each data memory 23 - j stores data related to processing in the arithmetic processor 2 .

FIG. 2 is a diagram for explaining the contents of the configuration memory 13 shown in FIG. 1 . As shown in FIG. 2, the configuration memory 13 stores configuration data and setting value data corresponding to each state. In FIG. 2, reference numeral CDi denotes configuration data; and CVDi denotes constant value data. Note that i is a suffix and is a (arbitrary) natural number from 1 to N. Referring to FIG. 2 , only the values of the constant value data CVDi are shown, and the values of the configuration data CDi are omitted.

When the kth (k is a suffix and a natural number from 1 to 128) state is to be set, the configuration data CDi and the fixed value data CVDi are provided to the arithmetic unit 22 - i and stored in the configuration register 24 . That is, configuration data and fixed value data related to a certain circuit configuration FUNCk for realizing a desired circuit function in the arithmetic processor 2 are composed of a pair of configuration data CD1 to CD1 arranged in the row direction shown in FIG. It consists of CDN and fixed value data CVD1 to CVDN. Note that, although not shown in FIG. 2 , the configuration memory 13 of course stores, for example, configuration data for controlling the selector/register 21 in addition to the configuration data related to the arithmetic unit 22 - i .

As described above, the reconfigurable semiconductor device enables so-called dynamic reconfiguration by using the sequencer 1 instead of the CPU, so that for each clock, the circuit configuration (logic) can be dynamically reconfigured. For example, arithmetic processor 2 may execute function A during a certain clock cycle and execute function B different from function A during the next clock cycle based on configuration data (control signals) from sequencer 1 .

However, in the reconfigurable semiconductor device shown in FIGS. 1 and 2, for an arithmetic unit capable of receiving a fixed value (constant), the fixed value data is stored in the configuration memory 13 together with the configuration data, and the fixed value is saved when necessary. Value data is read and stored in the configuration register 24 corresponding to the arithmetic unit. In order to store the fixed value data in the configuration memory 13 as described above, it is necessary to form a fixed value data area for storing the fixed value data in each arithmetic unit capable of receiving the fixed value data, and to store all the fixed value data in the configuration memory 13. If the width of the second input data from the selector/register 21 to the arithmetic unit capable of receiving fixed-value data is 32 bits, it must be configured in the configuration memory 13 for each arithmetic unit of the arithmetic processor 2 and for all states ( Also referred to as "configuration" hereinafter) form a 32-bit fixed-value data area.

However, it is hardly necessary to set fixed-value data as an input to each arithmetic unit for all states of the arithmetic processor 2, that is, it is hardly necessary to set constant value data as an input to each arithmetic unit whenever the state of the arithmetic processor 2 is switched. fixed value data. Therefore, the fixed value data area formed as described above wastes the storage area of the configuration memory 13, so that when the fixed value data is to be stored in the configuration memory 13, a large amount of memory (storage area) is consumed.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a diagram showing an arrangement example of a reconfigurable semiconductor device according to an embodiment of the present invention. In FIG. 3 , the same reference numerals as in FIG. 1 denote constituent elements having the same functions, and repeated explanations thereof will be omitted.

As shown in FIG. 3, the reconfigurable semiconductor device according to the present embodiment has a sequencer (controller) 1 and an arithmetic processor 2A. The arithmetic processor 2A includes a constant value memory (RAM) 30 for storing constant value data.

The sequencer 1 has a state controller 11 , a state register 12 and a configuration memory 13A.

The configuration memory 13A stores configuration data for setting the circuit configuration of the arithmetic processor 2A, and setting value designation data. The fixed value specifying data is information by which the fixed value data in the fixed value memory 30 that corresponds to the state of the arithmetic processor 2A can be uniquely identified. The fixed value designation data is used to designate and read out the fixed value data corresponding to the state of the arithmetic processor 2A from among the fixed value data stored in the fixed value memory 30 . Note that, in the following explanation, the fixed value specifying data is an address in the fixed value memory 30 .

Arithmetic processor 2A has selector/register (bus) 21 , arithmetic unit 22A-i, data memory 23 - j , fixed value memory 30 , selector 31 - i and fixed value specifying register 32 . Note that i and j are suffixes, i is an (arbitrary) natural number from 1 to N, and j is an (arbitrary) natural number from 1 to M.

The fixed value memory 30 is a memory for storing fixed value data. Based on the address value set by the sequencer 1 in the fixed value specifying register 32, the fixed value data stored in the fixed value memory 30 is read out and output to the selector 31-i.

The selector 31-i is controlled by the configuration data provided by the sequencer 1, and the selector 31-i selectively converts the second input data DT2 provided from the selector/register 21, or from the fixed value memory 30. The supplied constant value data CVD is output to the ALU unit 27 in the arithmetic unit 22A-i. More specifically, when the selector 31-i is set to output fixed value data by configuration data, it outputs the fixed value supplied from the fixed value memory 30 via the terminal assigned to the arithmetic unit 22A-i in the fixed value memory 30. Value data CVD. When the selector 31 - i is set to output the second input data DT2 by the configuration data, it outputs the second input data DT2 supplied from the selector/register 21 .

Each arithmetic unit 22A-i has a configuration register 25A and an ALU unit 27 . In the present embodiment, fixed value data is read out from the fixed value memory 30 to the ALU unit 27 via the selector 31-i. Therefore, in each arithmetic unit 22A-i, the configuration register 25A is the only register and, therefore, the constant value registers shown in FIG. 1 are not used.

Note that the configuration data and setting designation data stored in the configuration memory 13A and the setting data stored in the setting memory 30 are obtained from, respectively, before the operation starts, for example, using a RISC (processor) or other hardware. externally written and saved to the configuration memory 13A and the constant value memory 30. Note also that, for each state, configuration data and setting designation data are stored as a pair of data in the configuration memory 13A.

4A and 4B are diagrams for explaining the contents of configuration memory 13A and constant value memory 30 shown in FIG. 3 . For comparison purposes, FIGS. 4A and 4B show contents equivalent to those of the configuration memory 13 shown in FIG. 2 .

FIG. 4A shows the contents of the configuration memory 13A. In FIG. 4A, reference notation CDi (i=1 to N (natural number)) denotes configuration data; and CVAD denotes an address value in the constant value memory 30 as constant value specifying data.

FIG. 4B shows the contents of the constant value memory 30 . In FIG. 4B, reference numeral CVAD denotes an address value in the constant value memory 30; and CVDi (i=1 to N (natural number)) denotes constant value data.

As shown in FIG. 4B, in the fixed value memory 30, the same combination of fixed value data CVDi is not stored individually, but is stored as a set of fixed value data CVDi. That is, the combinations of fixed value data CVDi stored in the fixed value memory 30 are different from each other and do not overlap.

Moreover, as shown in FIG. 4A, only the configuration data CDi and the address value CVAD in the constant value memory 30 are stored in the configuration memory 13A, and the combination of the constant value data CVDi corresponding to this state is stored in the constant value memory 30. .

The operation of the reconfigurable semiconductor device according to this embodiment will be explained below. Note that the operation of the reconfigurable semiconductor device of this embodiment is the same as that of the reconfigurable semiconductor device shown in FIGS. Same, therefore, the explanation of the operation of the rest will be omitted.

The operation at the time of inputting fixed-value data to the arithmetic units in the arithmetic units 22A-i will be described below.

First, to switch the state of the arithmetic processor 2, the configuration data and setting designation data corresponding to the state are read out from the configuration memory 13A. The read configuration data is supplied to the functional units in the arithmetic processor 2A including the selector 31-i. The read fixed value designation data is provided to and set in the fixed value designation register 32 .

Based on the fixed value designation data set in the fixed value designation register 32, the fixed value data stored in the area designated by the fixed value designation data is read out from the fixed value memory 30, and is selected via the selector 31-i. It is output to arithmetic unit 22A-i. In this manner, fixed value data is supplied to arithmetic units in arithmetic units 22A-i.

The present embodiment described above uses a constant value memory 30 . However, as shown in Fig. 5, multiple constant value memories may also be used.

FIG. 5 is a diagram showing another arrangement example of the reconfigurable semiconductor device according to the present embodiment. In FIG. 5 , the same reference numerals as in FIGS. 1 and 3 denote constituent elements having the same functions, and repeated explanations thereof will be omitted.

The reconfigurable semiconductor device shown in FIG. 5 has a sequencer (controller) 1 and an arithmetic processor 2A. Arithmetic processor 2A includes two fixed-value memories (RAM) 30A and 30B.

The sequencer 1 has a state controller 11, a state register 12 and a configuration memory 13B. The configuration memory 13B stores configuration data, and two setting designation data corresponding to the setting memories 30A and 30B.

The arithmetic processor 2A is different from that shown in FIG. 3 in that it has two fixed value memories 30A and 30B, and two fixed value designation registers 32A and 32B corresponding to the fixed value memories 30A and 30B. However, the fixed value memories 30A and 30B, and the fixed value designation registers 32A and 32B respectively have the same functions as the fixed value memory 30 and the fixed value designation register 32 shown in FIG. 3, and thus detailed description thereof will be omitted.

6A to 6C are diagrams for explaining the contents of the configuration memory 13B and the constant value memories 30A and 30B shown in FIG. 5 . For comparison purposes, FIGS. 6A to 6C show equivalents to those shown in FIGS. 4A and 4B .

FIG. 6A shows the contents of the configuration memory 13B. In FIG. 6A, notation CDi (i=1 to N (natural number)) denotes configuration data; and CVAD1 and CVAD2 denote address values in fixed value memories 30A and 30B, respectively.

6B and 6C show the contents of the constant value memories 30A and 30B, respectively. In FIGS. 6B and 6C, reference numerals CVAD1 and CVAD2 denote address values in the constant value memories 30A and 30B, respectively; and CVDi (i=1 to N (natural numbers)) denote constant value data. Note that FIGS. 6B and 6C show a case where constant value data CVD1 and CVD3 are stored in the constant value memory 30A, and constant value data CVD2 and CVDN are stored in the constant value memory 30B.

Similar to the case shown in FIG. 4B , the same combination of constant value data CVDi is stored as a pair of constant value data CVDi in each of the constant value memories 30A and 30B.

Moreover, as shown in FIG. 6A, configuration memory 13B stores configuration data CDi, and address values CVAD1 and CVAD2 in fixed value memories 30A and 30B, respectively. Combination of corresponding fixed value data CVDi.

In FIGS. 5 and 6A to 6C, a case where two constant value memories 30A and 30B are used is shown as an example. However, the number of fixed value memories is an arbitrary number. Moreover, if no specific arithmetic unit always corresponds to a plurality of fixed-value memories, the correspondence between the fixed-value memories and the arithmetic units is an arbitrary correspondence. For example, one arithmetic unit may correspond to one fixed-value memory, or each of a plurality of groups obtained by dividing the arithmetic unit may correspond to one fixed-value memory.

Also, the arrangements shown in Figures 5 and 6A to 6C are not necessarily optimal arrangements. Therefore, the arrangements shown in FIGS. 3 , 4A, and 4B, or the arrangements shown in FIGS. 5 and 6A to 6C can be appropriately selected according to the application used.

In the present embodiment as described above, the fixed value data are stored in the fixed value memory 30 (30A and 30B), and the configuration data, and the fixed value used to read the fixed value data corresponding to the state of the configured data The address values of the memory are stored in the configuration memory 13A (13B). In the fixed value memories 30 (30A and 30B), only different combinations of fixed value data are stored in order to avoid duplication.

Therefore, the configuration memory only needs to store the address value of the fixed value memory without storing any fixed value data. This reduces the storage capacity required for the configuration memory and reduces the chip size. For example, in order to store eight different combinations of fixed value data in the fixed value memory, three bits can be used to represent the address value. This way, the storage area can be used very efficiently.

In addition, the constant value memory does not store constant value data for each state, but stores the same combination of constant value data as a pair of constant value data. This greatly reduces the amount of data. Also, fixed value data is stored in the fixed value memory, and this fixed value data can be supplied to the ALU unit 27 via the selector 31-i. In this way, the fixed value register can be omitted, and the circuit scale can be reduced.

Note that in the above embodiments, only one configuration register 25 is shown as an example. However, configuration registers are usually formed in a one-to-one correspondence with arithmetic units. Since the setting data are not provided via any registers, it is also possible to form a configuration register 25 for a plurality of arithmetic units.

Note also that the arrangement of the reconfigurable semiconductor device according to the present embodiment shown in the drawings is just an example. Therefore, the reconfigurable semiconductor device may also include shift registers, counter circuits, and memories such as RAM and ROM.

The above embodiments are merely implementation examples when the present invention is carried out, and thus the technical scope of the present invention should not be limitedly interpreted using these embodiments. That is, the present invention can be implemented in various forms without departing from the technical idea or main features of the present invention.

In the present invention, a fixed value memory different from a configuration memory for storing configuration information stores fixed values to be supplied to the arithmetic unit group. Since there is no need to set a data area for storing a fixed value in the configuration memory, a predetermined fixed value can be supplied to the arithmetic unit only by storing information for reading the fixed value from the fixed value memory in the configuration memory Group. Therefore, the storage capacity required for the configuration memory can be reduced, so that the configuration memory can be formed with a small-sized memory.

Also, since the constant values are stored in a constant value memory different from the configuration memory, there is no need to store constant values for each state of the arithmetic processor, and the constant value registers can be omitted. Therefore, it is possible to reduce the storage capacity required to store a fixed value, and to reduce the circuit scale.

This application is based on and claims priority from prior Japanese Patent Application No. 2004-194104 filed on June 30, 2004, the entire contents of which are hereby incorporated by reference.

Claims (12)

1. semiconductor devices comprises:

Config memory, described config memory store configuration information;

The arithmetical unit group, described arithmetical unit group has a plurality of arithmetical units, and can circuit arrangement be reshuffled according to the configuration information that provides from described config memory; With

Fixed value memory, described fixed value memory is stored the definite value that will be used in the arithmetic processing in the described arithmetical unit group, and the definite value of being stored is provided to described arithmetical unit group.

2. device according to claim 1, wherein, described config memory is stored the definite value appointed information together with described configuration information, and described definite value appointed information is used for obtaining and the corresponding definite value of described configuration information from described fixed value memory.

3. device according to claim 2, also comprise definite value appointed information register, the described definite value appointed information that described definite value appointed information register holds is read together with described configuration information from described config memory, and described definite value appointed information offered described fixed value memory.

4. device according to claim 2, wherein, described definite value appointed information is the address information of described fixed value memory, the zone of described address information indication storage and the corresponding definite value of described configuration information.

5. device according to claim 1 also comprises selector switch, and described selector switch optionally will offer described arithmetical unit group from definite value or the input value different with described definite value that described fixed value memory provides according to described configuration information.

6. device according to claim 5, wherein, described selector switch is placed on described arithmetical unit group and is connected between the bus of described arithmetical unit group, and the described selector switch definite value that optionally will provide from described fixed value memory or offer described arithmetical unit group from the input value of described bus.

7. device according to claim 1, wherein, described semiconductor devices comprises a plurality of described arithmetical unit groups, and described fixed value memory is divided into an arbitrary number storer according to described a plurality of arithmetical unit groups.

8. device according to claim 1, wherein, described semiconductor devices comprises a plurality of described arithmetical unit groups and a plurality of described fixed value memory, and the definite value that provide of each reception from described a plurality of fixed value memories in described a plurality of arithmetical unit group.

9. device according to claim 8, wherein, described config memory is stored the definite value appointed information together with described configuration information, and described definite value appointed information is relevant with each fixed value memory, and is used for obtaining and the corresponding definite value of described configuration information from described a plurality of fixed value memories.

10. device according to claim 1, wherein, the processing capacity of the described arithmetical unit of described arithmetical unit group and the interconnected relationship that connects described arithmetical unit change according to described configuration information.

11. device according to claim 1 also comprises sequencer, described sequencer is controlled the change in the circuit arrangement of described arithmetical unit group, and manages the state of described arithmetical unit group.

12. an arithmetic device comprises:

Register, the configuration information that described register holds provides from outside sequencer; With

The arithmetical unit group, described arithmetical unit group has a plurality of arithmetical units, and can circuit arrangement be reshuffled according to the described configuration information of being preserved in the described register,

Wherein, the definite value that be used in the arithmetic processing of described arithmetical unit group provides from the outside.

Images