WO2024187629A1 - Method and apparatus for vector instruction table filling and lookup in processor, and electronic device - Google Patents

Abstract

The present disclosure provides a method and apparatus for vector instruction table filling and lookup in a processor, and an electronic device. The method comprises: configuring a vector instruction lookup table in a preset storage space of the processor, wherein the storage capacity of the vector instruction lookup table is the product of the number of items and the number of bits of storage items; determining table filling types corresponding to candidate vector registers waiting for table filling, wherein the table filling types comprise a first type and a second type, the first type is that the product of the register width and the maximum number of register groups is larger than or equal to the storage capacity, and the second type is that the product of the register width and the maximum number of register groups is smaller than the storage capacity; and using table filling rules corresponding to the table filling types to write first elements stored in target vector registers among the plurality of candidate vector registers into the vector instruction lookup table, and using a preset table lookup rule to acquire, from the vector instruction lookup table, a second element to be looked up, such that the performance of the processor can be improved.

Description

Method, device and electronic device for filling and looking up vector instruction tables in processors

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on the Chinese patent application with application number 202310225470.7 and application date March 10, 2023, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this application as a reference.

Technical Field

The present disclosure relates to the field of computer technology, and in particular to a method, device and electronic device for filling and looking up a table of vector instructions in a processor.

Background Art

With the development of big data and artificial intelligence technology, people have higher and higher requirements for the performance of data analysis applications and artificial intelligence algorithms, and have put forward higher and higher requirements for computer processing capabilities. Vector processing technology has become a hot topic of common concern in academia and industry. Vector processing technology is usually applied to vector functions. Vector functions refer to all algorithm functions in computer programs that use vector instructions and vector registers when implemented internally. By using vector instructions and vector registers, the internal calculation of the function is implemented in a data-parallel manner.

The table lookup method is an optimization method used in the computer program development process. By calculating some required numerical results in advance and storing them in a constant array, they are directly taken out of the array during runtime instead of being temporarily calculated, thereby saving computing overhead. The vector table lookup method refers to the table lookup method used in vector functions. The table entries of the vector table will be used for a period of time. For example, filling and looking up tables in vector registers occupy vector register resources and vector register ports. When the vector registers are not enough, data access between vector registers and memory is required frequently, which affects pipeline performance.

Summary of the invention

The present disclosure proposes a method, device and electronic device for filling and looking up a table of vector instructions in a processor, aiming to solve one of the technical problems in the related art at least to a certain extent.

The first aspect of the present disclosure provides a method for filling and looking up a vector instruction table in a processor, comprising: configuring a vector instruction lookup table in a storage space preset by the processor, wherein the storage capacity of the vector instruction lookup table is the product of the number of items and the number of storage item bits; determining a table filling type corresponding to a candidate vector register to be filled in the table, wherein the table filling type includes a first type and a second type, the first type being that the product of the register width and the maximum number of register groups is greater than or equal to the storage capacity, and the second type being that the product of the register width and the maximum number of register groups is less than the storage capacity; using a table filling rule corresponding to the table filling type, writing a first element stored in a target vector register among multiple candidate vector registers into the vector instruction lookup table; and using a preset table lookup rule, obtaining a second element to be queried from the vector instruction lookup table.

The second aspect of the present disclosure provides a vector instruction table filling and table lookup device in a processor, including: a configuration module, used to configure a vector instruction lookup table in a storage space preset by the processor, wherein the storage capacity of the vector instruction lookup table is the product of the number of items and the number of storage item bits; a determination module, used to determine the table filling type corresponding to the candidate vector register to be filled in the table, wherein the table filling type includes a first type and a second type, the first type being that the product of the register width and the maximum number of register groups is greater than or equal to the storage capacity, and the second type being that the product of the register width and the maximum number of register groups is less than the storage capacity; a table filling module, used to write the first element stored in a target vector register among multiple candidate vector registers into the vector instruction lookup table using a table filling rule corresponding to the table filling type; and a table lookup module, used to obtain the second element to be queried from the vector instruction lookup table using a preset table lookup rule.

An embodiment of the third aspect of the present disclosure proposes an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the vector instruction table filling and table lookup method in the processor of the embodiment of the present disclosure.

The fourth aspect embodiment of the present disclosure proposes a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable the computer to execute the vector instruction table filling and table lookup method in the processor disclosed in the embodiment of the present disclosure.

The fifth aspect embodiment of the present disclosure proposes a computer program product, including a computer program, which, when executed by a processor, implements the vector instruction table filling and table lookup method in the processor disclosed in the embodiment of the present disclosure.

In the disclosed embodiment, a vector instruction lookup table is configured in a storage space preset by a processor, wherein the storage capacity of the vector instruction lookup table is the product of the number of items and the number of storage item bits, and a table filling type corresponding to a candidate vector register to be filled in the table is determined, wherein the table filling type includes a first type and a second type, wherein the first type is that the product of the register width and the maximum number of register groups is greater than or equal to the storage capacity, and the second type is that the product of the register width and the maximum number of register groups is less than the storage capacity, and a table filling rule corresponding to the table filling type is used to write a first element stored in a target vector register among multiple candidate vector registers into the vector instruction lookup table, and a preset table lookup rule is used to obtain a second element to be queried from the vector instruction lookup table, thereby reducing the occupancy of the vector register space and the register port, reducing the number of memory accesses, and utilizing the table filling rules and table lookup rules corresponding to the table filling type to quickly perform table filling and table lookup operations, thereby improving processor performance.

Additional aspects and advantages of the present disclosure will be given in part in the following description and in part will be obvious from the following description or learned through practice of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and/or additional aspects and advantages of the present disclosure will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

FIG1 is a flow chart of a method for filling and looking up a table of vector instructions in a processor according to an embodiment of the present disclosure;

FIG2A is a schematic diagram of the structure of a 256-bit width vector register provided according to an embodiment of the present disclosure;

FIG2B is a schematic diagram of the structure of a vector instruction lookup table corresponding to the vector register in FIG2A ;

FIG3A is a schematic diagram of the structure of a vector register with a width of 128 bits provided according to an embodiment of the present disclosure;

FIG3B is a schematic diagram of the structure of a vector instruction lookup table corresponding to the vector register in FIG3A ;

FIG4A is a schematic diagram of the structure of another 256-bit width vector register provided according to an embodiment of the present disclosure;

FIG4B is a schematic diagram of the structure of a vector instruction lookup table corresponding to the vector register in FIG4A ;

5 is a schematic diagram of a flow chart of a method for filling and looking up a table of vector instructions in a processor according to another embodiment of the present disclosure;

6 is a schematic flow chart of a method for filling and looking up a table of vector instructions in a processor according to another embodiment of the present disclosure;

7 is a schematic diagram of a vector instruction table filling and table lookup device in a processor according to another embodiment of the present disclosure;

FIG8 shows a block diagram of an exemplary electronic device suitable for implementing embodiments of the present disclosure.

DETAILED DESCRIPTION

In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

It should be noted that the executor of the method for filling and looking up a table of vector instructions in the processor of the embodiment of the present disclosure may be a device for filling and looking up a table of vector instructions in the processor, which may be implemented by software and/or hardware, and which may be configured in an electronic device, which may include but is not limited to a terminal, a server, etc.

FIG1 is a flow chart of a method for filling and looking up a table of vector instructions in a processor according to an embodiment of the present disclosure. As shown in FIG1 , the method includes steps S101 to S103 .

S101: configuring a vector instruction lookup table in a storage space preset by a processor.

In the embodiment of the present disclosure, an independent storage space may be set on the processor chip, and a vector instruction lookup table (also referred to as a lookup table, Table) may be configured in the storage space. The vector instruction lookup table is used to store elements in the vector register.

[Corrected 29.06.2023 in accordance with Article 91]
The vector instruction lookup table includes M storage items, each storage item is used to store an element of the vector instruction, and each storage item has a corresponding storage item bit number N. The number of items M of the storage items is equal to the index bit width of the vector lookup table index to the power of 2, that is, M = 2 ^{index bit width} , and the number of storage item bits N is equal to the effective element width (EEW) of the element (destination operand) written into the vector instruction lookup table, that is, N = destination operand EEW. In the embodiment of the present disclosure, the EEW can be configured to be equal to the actual element width SEW of the vector register to be operated, for example, SEW = 8, then each storage item has a corresponding storage item bit number N of 8 bits. In addition, the embodiment of the present disclosure can calculate the product of the number of storage items M and the number of storage items N as the storage capacity of the vector instruction lookup table, that is, storage capacity = M*N.

In one embodiment, Figure 2A is a structural diagram of a 256-bit wide vector register provided according to an embodiment of the present disclosure, and Figure 2B is a structural diagram of a vector instruction query table corresponding to the vector register in Figure 2A. As shown in Figure 2B, the vector instruction query table (Table) configured in the embodiment of the present disclosure is, for example, 256 items (i.e., M=256), including a0, a1, ..., a255 storage items; each SEW is an 8-bit integer, i.e.: N=8, then the storage capacity of the vector instruction query table = 256*8=2048 bits, SEW is other values, and so on.

S102: Determine the table filling type corresponding to the candidate vector register to be filled.

Among them, all vector registers supported by the processor can be called candidate vector registers. For example, the 32 vector registers (v0-v31) included in the RISC-V vector instruction set can be called candidate vector registers. That is to say, there are multiple candidate vector registers in the embodiment of the present disclosure.

In practical applications, the candidate vector registers may be configured with different register widths (VLEN), where VLEN may be, for example, 64 bits, 128 bits, 256 bits, 512 bits, and so on.

For example, as shown in Figure 2A, the RISC-V vector instruction set includes 32 candidate vector registers (v0-v31), and the register width VLEN of each vector register is 256 bits (0-255), that is: a 256-bit vector register, where each vector register stores 32 elements, for example, v16 stores a0-a31 elements, the SEW of each element is 8 bits, and the number of registers in each group LMUL is 8.

For another example, Figure 3A is a structural diagram of a 128-bit wide vector register provided according to an embodiment of the present disclosure. As shown in Figure 3A, the register width VLEN of each vector register in the 32 candidate vector registers (v0-v31) is 128 bits (0-127), that is: a 128-bit vector register, wherein each vector register stores 16 elements, for example, v16 stores a0-a15 elements, the SEW of each element is 8 bits, and the number LMUL of each group of registers is 8.

In the embodiment of the present disclosure, for determining candidate vector registers of different register widths VLEN, it is necessary to determine the corresponding table filling type. The table filling type of the embodiment of the present disclosure includes, for example, a first type and a second type.

The disclosed embodiment can calculate the product of the register width VLEN of the candidate vector register and the maximum number of register groups (the maximum number of registers in the register group LMUL), that is: VLEN*maximum LMUL, and further determine the size relationship between VLEN*maximum LMUL and the storage capacity (M*N) of the vector instruction query table, wherein the first type is that the product of the register width VLEN and the maximum number of register groups is greater than or equal to the storage capacity, and the second type is that the product of the register width VLEN and the maximum number of register groups is less than the storage capacity. It should be noted that in the RISC-V vector instruction set, the maximum number of register groups LMUL is 8.

For example, the storage capacity (M*N) is 2048 bits, the register width VLEN of the candidate vector register shown in FIG2A is 256, the maximum number of register groups LMUL is 8, VLEN*maximum LMUL is equal to M*N, and the table filling type corresponding to the 256-bit candidate vector register is the first type; for another example, the register width VLEN of the candidate vector register shown in FIG3A is 128, the maximum number of register groups LMUL is 8, VLEN*maximum LMUL is less than M*N, and the table filling type corresponding to the 128-bit candidate vector register is the second type.

After configuring the vector instruction query table as described above, the embodiment of the present disclosure can further determine the table filling type corresponding to the candidate vector register, that is, the first type or the second type.

S103: Using a table filling rule corresponding to the table filling type, write the first element stored in the target vector register among the plurality of candidate vector registers into the vector instruction lookup table.

Among them, the table filling rule can also be called a vector table filling instruction (table_fill), which is used to write the first element stored in the target vector register among multiple candidate vector registers into the vector instruction query table, that is, to fill the first element into the corresponding item of the vector instruction query table.

The register in the plurality of candidate vector registers that needs to be written (filled) into the vector instruction query table Table may be referred to as a target vector register, and the target vector register may be one vector register or multiple vector registers (i.e., a group of vector registers), that is, the embodiment of the present disclosure may determine one vector register or a group of vector registers as the target vector register for writing into the vector instruction query table Table. The target vector register may be determined in any possible manner.

The element (data) in the target vector register that needs to be written into the vector instruction query table Table can be called the first element, that is, the content (element) in the target vector register is filled into the vector instruction query table Table. Wherein, in the case where the target vector register is a plurality of vector registers, the first element can be all elements stored in the plurality of target vector registers; or, in the case where the target vector register is a single vector register, the first element can be all elements or part of the elements in the target vector register.

In the disclosed embodiment, different table filling rules can be configured for different table filling types, that is, the first type and the second type of candidate vector registers correspond to different table filling rules, and the present implementation can use the table filling rules corresponding to the table filling type to determine the target vector register, and write the first element stored in the target vector register into the vector instruction query table. The specific content of the table filling rules is not specifically limited here.

In some embodiments, a preset table lookup rule may be used to obtain the second element to be queried from the vector instruction lookup table, and the second element may be written into a preset vector destination register.

Among them, the element currently required to be queried in the vector instruction query table Table can be called the second element, that is, the second element belongs to the first element, and the second element can be one element or multiple elements.

In the embodiment of the present disclosure, a table lookup rule (also referred to as a vector table lookup instruction) can be pre-configured, and the table lookup rule is used to obtain the second element from the vector instruction lookup table. That is to say, the embodiment of the present disclosure can directly read the vector element from the vector instruction lookup table without reading the vector element from the vector register, thereby reducing the occupation of the vector register space and register port and reducing the number of memory accesses. The table lookup rule can be an arbitrary rule. In some embodiments, the form of the table lookup rule (i.e., table lookup instruction) can be recorded as: table_find.v vdest, vidx, wherein table_find.v represents a vector table lookup in the vector instruction set, vidx represents a vector index register, and vdest represents a vector destination register.

In some embodiments, the table lookup rule may be to first determine a vector index register vidx, for example, a register may be randomly selected from a plurality of candidate vector registers as the vector index register vidx.

Further, the index bit width is determined according to the number of items M of the vector instruction lookup table, that is, the index bit width is determined according to ^{the index bit width} M=2. For example, the number of items of the vector instruction lookup table in the embodiment of the present disclosure is 256 items (that is, M=256), that is: 256=2 ⁸ , that is, the index bit width of the vector instruction lookup table in the embodiment of the present disclosure is 8 bits.

Further, the ratio of the register width VLEN of the vector index register vidx to the index bit width is calculated as the number of indexes. For example, as shown in Figures 2A and 2B, the register width of a vector index register vidx randomly selected from multiple candidate vector registers is 256 bits, and the number of indexes is 32, that is, the 256-bit vector index register vidx can be divided into 32 8-bit indexes, represented as idx0, idx1, idx2, idx3, ..., idx29, idx30, idx31; for another example, as shown in Figures 3A and 3B, the register width of a vector index register vidx randomly selected from multiple candidate vector registers is 128 bits, and the number of indexes is 16, that is, the 128-bit vector index register vidx is divided into 16 8-bit indexes, represented as idx0, idx1, idx2, idx3, ..., idx29, idx30, idx15.

Furthermore, the disclosed embodiment performs a parallel lookup of the vector instruction lookup table based on the number of indexes and the target index value to be queried to obtain a second element corresponding to the target index value. Specifically, the first element in the vector instruction lookup table may have a corresponding index value, such as the sequence number of the storage item, for example, if there are 256 storage items, the index values are 0, 1, 2, ..., 255 in sequence, and the index value corresponding to the current element to be queried may be referred to as the target index value, and the element corresponding to the target index value found may be referred to as the second element.

For example, as shown in FIGS. 2A and 2B , the 256-bit vector index register vidx of the embodiment of the present disclosure is divided into 32 8-bit indexes idx0, idx1, idx2, idx3, ..., idx29, idx30, idx31, and the target index values are, for example, {254, 251, 250, ..., 7, 5, 3, 2}, totaling 32. Then, the embodiment of the present disclosure can use 32 8-bit indexes to perform parallel lookup on the 32 target index values in the vector instruction lookup table, idx0, idx1, idx2, idx3, ..., idx29, idx30 , idx31 are 2 (binary 00000010), 3 (binary 00000011), 5 (binary 00000101), 7 (binary 00000111), ..., 250 (binary 11111010), 251 (binary 11111011), 254 (binary 11111110), that is, the 32 second elements found in parallel from the vector instruction query table Table according to the index vidx are a2, a3, a5, a7, ..., a250, a251, a254, each element is 8 bits.

For another example, as shown in FIGS. 3A and 3B , the 128-bit vector index register vidx in the embodiment of the present disclosure is divided into 16 8-bit indexes idx0, idx1, idx2, idx3, ..., idx15, and the target index values are, for example, {254, 251, 122, ..., 7, 5, 3, 2}, totaling 16. Then, the embodiment of the present disclosure can use 16 8-bit indexes to perform parallel lookup on the 16 target index values in the vector instruction lookup table, and idx0, idx1, idx2, idx3, ..., idx15 are 2 (two In other words, the 16 second elements found in parallel from the vector instruction lookup table Table according to the index vidx are a2, a3, a5, a7, ..., a250, a251, a254, and each element is 8 bits.

Furthermore, the embodiment of the present disclosure writes the second element into a preset vector destination register. For example, any one register (e.g., v25) can be selected from a plurality of candidate vector registers as the vector destination register, which can be represented by vdest, and the embodiment of the present disclosure can write the acquired second element into the vector destination register vdest to complete the vector table lookup operation. For example, the 32 second elements a2, a3, a5, a7, ..., a250, a251, a254, etc., which are queried, are written back to the vector destination register vdest (for example, v25), and the value of the vector destination register vdest is {a254, a251, a250, ..., a7, a5, a3, a2}; for another example, the 16 second elements a2, a3, a5, a7, ..., a250, a251, a254, etc. are written back to the vector destination register vdest (for example, v25), and the value of the vector destination register vdest is {a254, a251, a250, ..., a7, a5, a3, a2}.

In some embodiments, the vector index register vidx and the vector destination register vdest need to have the same number of elements, but the element widths may be different. In this case, the EEW and EMUL (the number of registers in the register group when the element width in the register is EEW) of the vector index register vidx and the vector destination register vdest are not equal to SEW and LMUL, but EEW/EMUL=SEW/LMUL, so as to ensure that the number of elements is the same. For example, the EEW of the vector index register vidx is SEW, and EMUL is LMUL, but the EEW of the vector destination register vdest is 2*SEW, and EMUL is 2*LMUL, that is, the element width of the vector index register vidx is different from the element width of the vector destination register vdest. In this case, in the process of writing the second element into a preset vector destination register in the embodiment of the present disclosure, the size relationship between the element width of the vector destination register vdest and the element width of the vector index register vidx can be determined. When the element width of the vector destination register is greater than the element width of the vector index register, and the element width of the vector destination register is the same as the number of storage item bits, the table lookup instruction of the embodiment of the present disclosure is a widening instruction, and the number of vector destination registers is determined according to the above-mentioned EEW/EMUL=SEW/LMUL relationship, that is: a group of multiple vector destination registers vdest, wherein the number of a group of vector destination registers EMUL=EEW*LMUL/SEW; further, the second element is written into multiple vector destination registers.

For example, Figure 4A is a structural diagram of another 256-bit width vector register provided according to an embodiment of the present disclosure, and Figure 4B is a structural diagram of a vector instruction query table corresponding to the vector register in Figure 4A. As shown in Figure 4B, the vector instruction query table (Table) configured in the embodiment of the present disclosure is, for example, 256 items (i.e., M=256), including a0, a1,..., a255 storage items; each SEW is a 16-bit integer, i.e.: N=16, then the storage capacity of the vector instruction query table = 256*16=4096 bits, SEW is other values, and so on. As shown in Figures 4A and 4B, the register width VLEN of a vector index register vidx (LMUL = 1) is 256 bits, the element width EEW = SEW = 8 bits per element, M = 256 items, N = 16 bits, the element width EEW = 16 of the vector destination register vdest, then the number of vector destination registers EMUL = EEW * LMUL / SEW = 16 * 1 / 8 = 2, that is, a group of 2 vector destination registers, such as v24 and v25. The 32 elements found in parallel from the Table according to the index vidx are b2, b3, b5, b7, ..., b250, b251, b254, each element is 16 bits, and are written back to the vector destination registers v24 and v25. The value of the vector destination register v24 is {…, b7, b5, b3, b2}, and the value of the vector destination register v25 is {b254, b251, b250, …}, completing the vector table lookup. In Figures 4A and 4B, _low and _high represent the lower 8 bits and higher 8 bits of the element, respectively.

In practical applications, the table lookup instruction can be recorded as table_find.v vdest,vidx, where vdest represents the vector destination register and vidx represents the vector index register. For example, if vidx is v24 and vdest is v25, the table lookup instruction is table_find.v v25,v24.

In the disclosed embodiment, a vector instruction lookup table is configured in a storage space preset by a processor, wherein the storage capacity of the vector instruction lookup table is the product of the number of items and the number of storage item bits, and a table filling type corresponding to a candidate vector register to be filled in the table is determined, wherein the table filling type includes a first type and a second type, wherein the first type is that the product of the register width and the maximum number of register groups is greater than or equal to the storage capacity, and the second type is that the product of the register width and the maximum number of register groups is less than the storage capacity, and a table filling rule corresponding to the table filling type is used to write a first element stored in a target vector register among multiple candidate vector registers into the vector instruction lookup table, and a preset table lookup rule is used to obtain a second element to be queried from the vector instruction lookup table, thereby reducing the occupancy of the vector register space and the register port, reducing the number of memory accesses, and utilizing the table filling rules and table lookup rules corresponding to the table filling type to quickly perform table filling and table lookup operations, thereby improving processor performance.

FIG5 is a flow chart of a method for filling and looking up a table of vector instructions in a processor according to an embodiment of the present disclosure. As shown in FIG5 , the method includes steps S501 to S506 .

S501: configuring a vector instruction lookup table in a storage space preset by a processor.

S502: Determine the table filling type corresponding to the candidate vector register to be filled.

The specific description of S501 - S502 refers to the above embodiment and will not be repeated here.

S503: Calculate a ratio of the storage capacity to the register width of the candidate vector register to serve as a first number of registers in the register group.

In the embodiment of the present disclosure, the table filling type corresponding to the candidate vector register is the first type. In this case, the table filling rule of the embodiment of the present disclosure is to first calculate the ratio of the storage capacity to the register width (VLEN) of the candidate vector register, and use the ratio as the first number LMUL of the actual registers in the register group, that is, the first number LMUL=M*N/VLEN.

For example, if the width VLEN of the candidate vector register is 256 bits, M*N=2048, then the first number LMUL is 8, that is, LMUL=2048/256=8; for another example, if the width VLEN of the candidate vector register is 512 bits, then the first number LMUL is 4; for another example, if the width VLEN of the candidate vector register is 1024 bits, then the first number LMUL is 2; for another example, if the width VLEN of the candidate vector register is 2048 bits, then the first number LMUL is 1; for another example, if the width VLEN of the candidate vector register is 4096 bits, then the first number LMUL is 1/2, that is, 1/2 registers are a group; for another example, if the width VLEN of the candidate vector register is 8192 bits, then the first number LMUL is 1/4, that is, 1/4 registers are a group; for another example, if the width VLEN of the candidate vector register is 16384 bits, then the first number LMUL is 1/8, that is, 1/8 registers are a group, and so on.

S504: Determine a first number of registers from a plurality of candidate vector registers as target vector registers.

That is, a first number LMUL of registers are determined from the 32 candidate vector registers as a group of target vector registers, for example, 8 (LMUL) registers are selected as a group of target vector registers, or 4 registers are selected as a group of target vector registers, or 2 registers are selected as a group of target vector registers, etc. The target vector registers can be determined from the 32 candidate vector registers in any manner, for example, a group of target vector registers is randomly selected.

In some embodiments, in order to improve the efficiency of table filling and subsequent table lookup, the embodiments of the present disclosure may determine a continuous group of registers as target vector registers.

The disclosed embodiment can first determine the source register number from the numbers of multiple candidate vector registers, which can be represented by vsrc. For example, the numbers of 32 candidate vector registers are 0, 1, 2, ..., 31, and the disclosed embodiment can determine a source register number vsrc from the multiple numbers.

For example, the source register number vsrc may be any one of 0, 1, 2, ..., 31.

For another example, the source register number can be aligned with the first number LMUL. For example, if LMUL is 8, the source register number vsrc of the vector table filling instruction (table filling rule) is, for example, any one of 0, 8, 16, and 24; if LMUL is 4, the source register number vsrc of the vector table filling instruction is, for example, any one of 0, 4, 8, 12, 16, 20, 24, and 28; if LMUL is 2, the source register number vsrc of the vector table filling instruction is, for example, any one of 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, and 30; if LMUL is 1/8, 1/4, 1/2, or 1, the source register number vsrc of the vector table filling instruction can be any register number.

Further, a first number of registers consecutively starting from the source register number is determined as the target vector registers.

For example, as shown in Figures 2A and 2B, the register width VLEN is 256 bits, LMUL is 8, and the source register number vsrc is, for example, 16 (ie, v16). Then, the eight consecutive registers starting from number 16 can be determined as a group of target vector registers, that is, the target vector registers are v16 to v23.

S505: Write the first element stored in the target vector register into the vector instruction lookup table.

In practical applications, the table filling rules (table filling instructions) corresponding to the first type can be pre-configured, recorded as table_fill.v vsrc, where table_fill.v represents the table filling of the vector in the vector instruction set, and vsrc represents the source register number. For example, if the source register number vsrc is 16, the table filling instruction is table_fill.v v16. Further, the table_fill.v v16 instruction is used to fill the elements a0-a255 (i.e., the first element) in a group of 8 target vector registers v16 to v23 into the 0th to 255th items of the vector instruction query table, that is, the number of the first elements of the target vector register in the embodiment of the present disclosure is the same as the number of items in the vector instruction query table. Therefore, the embodiment of the present disclosure can use the table filling rules to write elements in registers greater than or equal to 256 bits into the vector instruction query table.

S506: Obtain the second element to be queried from the vector instruction query table using a preset table query rule.

The specific description of S506 refers to the above embodiment and will not be repeated here.

In the embodiment of the present disclosure, by configuring a vector instruction query table in a storage space preset by a processor, wherein the storage capacity of the vector instruction query table is the product of the number of items and the number of bits of the storage items, and determining the table filling type corresponding to the candidate vector register to be filled in the table, wherein the table filling type includes a first type and a second type, wherein the first type is that the product of the register width and the maximum number of register groups is greater than or equal to the storage capacity, and the second type is that the product of the register width and the maximum number of register groups is less than the storage capacity, and using the table filling rules corresponding to the table filling type, the first element stored in the target vector register in multiple candidate vector registers is written into the vector instruction query table, and using the preset table lookup rules, the second element to be queried is obtained from the vector instruction query table, which can reduce the occupation of the vector register space and the register port, reduce the number of memory accesses, and use the table filling rules and table lookup rules corresponding to the table filling type to quickly perform table filling and table lookup operations, thereby improving processor performance. In addition, the embodiment of the present disclosure can use the table filling rules to write elements in registers greater than or equal to 256 bits into the vector instruction query table.

FIG6 is a flow chart of a method for filling and looking up a table of vector instructions in a processor according to an embodiment of the present disclosure. As shown in FIG6 , the method includes steps S601 to S606 .

S601: configuring a vector instruction lookup table in a storage space preset by a processor.

S602: Determine the table filling type corresponding to the candidate vector register to be filled.

The specific description of S601 - S602 refers to the above embodiment and will not be repeated here.

S603: Calculate the ratio of the storage capacity to the first target value as the number of form filling times.

The first target value is the product of the register width of the candidate vector register and the maximum number of register groups.

In the embodiment of the present disclosure, the table filling type corresponding to the candidate vector register is the second type. In this case, the table filling rule of the embodiment of the present disclosure is to first calculate the ratio of the storage capacity (M*N) to the first target value as the number of table fillings, wherein the first target value is the product (VLEN*maximum LMUL) of the register width VLEN of the candidate vector register and the maximum number of register groups (maximum LMUL=8), that is, the number of table fillings=M*N/VLEN*maximum LMUL.

Among them, the number of table filling times corresponds to the number of table filling instructions, and each table filling instruction can write the first element in a set of target vector registers into the vector instruction query table. That is to say, when the table filling type is the second type, multiple table filling instructions are required to perform multiple table filling operations.

For example, as shown in Figures 3A and 3B, if the storage capacity (M*N) of the vector instruction query table is 2048, the register width VLEN is 128, and the maximum LMUL is 8, then the number of table filling times (i.e., the number of table filling instructions) is M*N/VLEN*maximum LMUL=2048/128*8=2, that is, two table filling instructions are required to fill the table twice; for another example, if the storage capacity (M*N) of the vector instruction query table is 2048, the register width VLEN is 64, and the maximum LMUL is 8, then the number of table filling times (i.e., the number of table filling instructions) is 2048/64*8=4, that is, four table filling instructions are required to fill the table four times.

S604: Determine, from the plurality of candidate vector registers, a plurality of register groups having the same number of table filling times.

Each register group includes a second number of target vector registers. In the disclosed embodiment, the number of registers in each register group may be referred to as a second number (LMUL), which may be a fixed value, such as LMUL=8, that is, 8 target vector registers are regarded as a register group.

In the embodiment of the present disclosure, multiple register groups with the same number of table filling times can be determined from multiple candidate vector registers. For example, if the number of table filling times is 2, two register groups are determined, each register group includes 8 target vector registers. The multiple register groups can be determined in any manner, for example, 8 target vector registers are randomly selected as a register group.

In some embodiments, a plurality of source register numbers equal to the number of table fillings are determined from the plurality of candidate vector register numbers, wherein the interval between the source register numbers is at least a second number.

For example, the number of table filling operations is 2 times (i.e., 2 table filling instructions), and the multiple candidate vector registers are numbered 0, 1, 2, ..., 31. Then, the embodiment of the present disclosure can determine 2 numbers from the multiple numbers as source register numbers vsrc, wherein the interval between the two source register numbers vsrc is at least the second number (8), for example, the two source register numbers vsrc are 8 and 16 respectively.

Further, a second number of registers starting from each source register number is determined to constitute each register group. In other words, each source register number is used as the starting bit of a register group, and a second number of registers starting from the starting bit are determined as the target vector registers in the register group.

For example, the two source register numbers vsrc are 8 and 16 respectively, then the embodiment of the present disclosure may determine v8 to v15 as one register group, and determine v16 to v23 as another register group.

S605: Write the first element stored in the target vector register in each register group into the vector instruction lookup table in sequence.

That is to say, the disclosed embodiment may first write the first element stored in the target vector registers from v8 to v15 (register grouping) into the vector instruction lookup table, and then write the first element stored in the target vector registers from v16 to v23 (register grouping) into the vector instruction lookup table.

In some embodiments, during the table filling process, the embodiments of the present disclosure can also determine multiple offset numbers (also referred to as offsets) corresponding to multiple register groups, which can be represented by imm. The offset number imm is a non-negative integer, wherein the multiple offset numbers are integers from 0 to n in sequence, and n is the number of table fillings minus one, that is, the offset number imm takes values from 0 to M*N/VLEN*maximum LMUL-1.

For example, if VLEN is 128 bits and the value of LMUL is 8, the number of table fills is 2 (two table fill instructions are required to complete), and the offset numbers imm corresponding to the register groups are 0 and 1 respectively. That is to say, the offset number imm of the first table fill instruction is 0 (binary 00000000), and the offset number imm of the second table fill instruction is 1 (binary 00000001); for another example, if VLEN is 64 bits and the value of LMUL is also 8, the number of table fills is 4 ( 4 table filling instructions are required to complete), the offset numbers imm corresponding to the register groups are 0, 1, 2, and 3 respectively. That is to say, the offset number imm of the first table filling instruction is 0 (binary 00000000), the offset number imm of the second table filling instruction is 1 (binary 00000001), the offset number imm of the third table filling instruction is 2 (binary 00000010), and the offset number imm of the fourth table filling instruction is 3 (binary 00000011).

Further, the product of the offset number imm corresponding to each register group and the second target value is calculated as the starting fill bit of each register group in the vector instruction query table, and the starting fill bit can also be called the starting fill item, which is used to describe the starting item written by each register group in the vector instruction query table. Among them, the second target value is the ratio of the first target value (VLEN*maximum LMUL) to the number of storage item bits (N), that is, the starting fill bit = imm*VLEN*maximum LMUL/N.

For example, the number of storage item bits N=8, VLEN is 128 bits, and the corresponding offset numbers imm of the two register groups are 0 and 1. Then the starting fill bits of the first register group are 0*128*8/8=0, and the starting fill bits of the second register group are 1*128*8/8=128.

Further, based on the start fill bit, the first element stored in the target vector register in each register group is sequentially written into the vector instruction lookup table.

In practical applications, the table filling instructions corresponding to the second type can be recorded as: table_fill.v vsrc imm, where table_fill.v represents the vector table filling in the vector instruction set, vsrc represents the source register number, and imm represents the offset number. For example, VLEN is 128 bits, LMUL is 8, and the offset number imm is 0 and 1. If the source register number vsrc is the 8th and 16th vector registers, respectively, the two table filling instructions can be recorded as table_fill.v v8 0 and table_fill.v v161, that is, the table_fill.v v8 0 instruction is used to fill the first element a0-a127 in a group of 8 target vector registers from v8 to v15 into the 0th to 127th items of the vector instruction query table, and the table_fill.v v16,1 instruction is used to fill the elements a128-a255 in a group of 8 registers from v16 to v23 into the 128th to 255th items of the vector instruction query table. Therefore, the embodiment of the present disclosure can use the table filling rule to write elements in a register smaller than 256 bits into the vector instruction lookup table.

It should be noted that the table filling process and the table looking up process of the embodiment of the present disclosure may be performed sequentially or separately.

In the embodiment of the present disclosure, a vector instruction query table is configured in a storage space preset by a processor, wherein the storage capacity of the vector instruction query table is the product of the number of items and the number of bits of the storage items, and the table filling type corresponding to the candidate vector register to be filled in the table is determined, wherein the table filling type includes a first type and a second type, wherein the first type is that the product of the register width and the maximum number of register groups is greater than or equal to the storage capacity, and the second type is that the product of the register width and the maximum number of register groups is less than the storage capacity, and the table filling rules corresponding to the table filling type are used to write the first element stored in the target vector register in multiple candidate vector registers into the vector instruction query table, and the preset table lookup rules are used to obtain the second element to be queried from the vector instruction query table, which can reduce the occupation of the vector register space and the register port, reduce the number of memory accesses, and use the table filling rules and table lookup rules corresponding to the table filling type to quickly perform table filling and table lookup operations, thereby improving processor performance. In addition, the embodiment of the present disclosure can use the table filling rules to write elements in registers less than 256 bits into the vector instruction query table.

In order to implement the above embodiment, the present disclosure also proposes a vector instruction table filling and table lookup device in a processor.

FIG7 is a schematic diagram of a vector instruction table filling and table lookup device in a processor according to another embodiment of the present disclosure.

As shown in FIG. 7 , the vector instruction table filling and table lookup device 70 in the processor includes:

A configuration module 701 is used to configure a vector instruction query table in a storage space preset by the processor, wherein the storage capacity of the vector instruction query table is the product of the number of items and the number of storage item bits;

A determination module 702 is used to determine a table filling type corresponding to a candidate vector register to be filled in a table, wherein the table filling type includes a first type and a second type, the first type being that the product of the register width and the maximum number of register groups is greater than or equal to the storage capacity, and the second type being that the product of the register width and the maximum number of register groups is less than the storage capacity;

A table filling module 703 is used to write the first element stored in the target vector register among the plurality of candidate vector registers into the vector instruction lookup table by using a table filling rule corresponding to the table filling type; and

The table lookup module 704 is used to obtain the second element to be looked up from the vector instruction lookup table using a preset table lookup rule.

In some embodiments, when the table filling type is the first type, the table filling module 703 is specifically used to: calculate the ratio of the storage capacity to the register width of the candidate vector register as the first number of registers in the register group; determine a first number of registers from multiple candidate vector registers as target vector registers; and write the first element stored in the target vector register into the vector instruction query table.

In some embodiments, the table filling module 703 is specifically used to: determine a source register number from a plurality of candidate vector register numbers; and determine a first number of registers starting from the source register number and continuing as target vector registers.

In some embodiments, when the table filling type is the second type, the table filling module 703 is specifically used to: calculate the ratio of the storage capacity to the first target value as the number of table fillings, wherein the first target value is the product of the register width of the candidate vector register and the maximum number of register groups; determine a plurality of register groups with the same number of table fillings from a plurality of candidate vector registers, wherein each register group includes a second number of target vector registers; and write the first element stored in the target vector register in each register group into the vector instruction lookup table in turn.

In some embodiments, the table filling module 703 is specifically used to: determine a plurality of source register numbers with the same number of table filling times from the numbers of a plurality of candidate vector registers, wherein the interval between the source register numbers is at least a second number; and determine that a second number of consecutive registers starting from each source register number constitute each register group.

In some embodiments, the device 70 also includes: a first calculation module, used to determine multiple offset numbers corresponding to multiple register groups, wherein the multiple offset numbers are integers from 0 to n in sequence, and n is the number of table filling times minus one; a second calculation module, used to calculate the product of the offset number corresponding to each register group and the second target value as the starting fill bit of each register group in the vector instruction query table, wherein the second target value is the ratio of the first target value to the number of storage item bits; and a table filling module 703, specifically used to: based on the starting fill bit, write the first element stored in the target vector register in each register group into the vector instruction query table in sequence.

In some embodiments, the table lookup module 704 is specifically used to: determine a vector index register; determine the index bit width according to the number of items in the vector instruction lookup table; calculate the ratio of the register width of the vector index register to the index bit width as the number of indexes; perform parallel lookup on the vector instruction lookup table based on the number of indexes and the target index value to be queried to obtain a second element corresponding to the target index value; and write the second element into a preset vector destination register.

In some embodiments, when the element width of the vector destination register is greater than the element width of the vector index register, and the element width of the vector destination register is the same as the number of storage item bits, the table lookup module is specifically used to: determine multiple vector destination registers; and write the second element into the multiple vector destination registers.

In some embodiments, the form of the table filling rule corresponding to the first type is: table_fill.v vsrc, and the form of the table filling rule corresponding to the second type is: table_fill.v vsrc,imm; wherein table_fill.v represents the table filling for vectors in the vector instruction set, vsrc represents the source register number, and imm represents the offset number.

In some embodiments, the table lookup rule is in the form of: table_find.v vdest, vidx, where table_find.v represents a vector table lookup in a vector instruction set, vidx represents a vector index register, and vdest represents a vector destination register.

In the disclosed embodiment, a vector instruction lookup table is configured in a storage space preset by a processor, wherein the storage capacity of the vector instruction lookup table is the product of the number of items and the number of storage item bits, and a table filling type corresponding to a candidate vector register to be filled in the table is determined, wherein the table filling type includes a first type and a second type, wherein the first type is that the product of the register width and the maximum number of register groups is greater than or equal to the storage capacity, and the second type is that the product of the register width and the maximum number of register groups is less than the storage capacity, and a table filling rule corresponding to the table filling type is used to write a first element stored in a target vector register among multiple candidate vector registers into the vector instruction lookup table, and a preset table lookup rule is used to obtain a second element to be queried from the vector instruction lookup table, thereby reducing the occupancy of the vector register space and the register port, reducing the number of memory accesses, and utilizing the table filling rules and table lookup rules corresponding to the table filling type to quickly perform table filling and table lookup operations, thereby improving processor performance.

According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium, and a computer program product.

In order to implement the above embodiments, the present disclosure further proposes a computer program product. When an instruction processor in the computer program product is executed, the vector instruction table filling and table lookup method in the processor proposed in the above embodiments of the present disclosure is executed.

Fig. 8 shows a block diagram of an exemplary electronic device suitable for implementing the embodiments of the present disclosure. The electronic device 12 shown in Fig. 8 is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

As shown in Fig. 8, the electronic device 12 is in the form of a general purpose computing device. The components of the electronic device 12 may include, but are not limited to: one or more processors 16, a system memory 28, and a bus 18 connecting different system components (including the system memory 28 and the processor 16).

Bus 18 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor or a local bus using any of a variety of bus structures. For example, these architectures include but are not limited to Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MAC) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) local bus and Peripheral Component Interconnection (PCI) bus.

The electronic device 12 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by the electronic device 12, including volatile and non-volatile media, removable and non-removable media.

The memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and/or cache memory 32. The electronic device 12 may further include other removable/non-removable, volatile/non-volatile computer system storage media. By way of example only, the storage system 34 may be used to read and write non-removable, non-volatile magnetic media (not shown in FIG. 8 , commonly referred to as a “hard drive”).

Although not shown in FIG. 8 , a disk drive for reading and writing to a removable nonvolatile disk (e.g., a “floppy disk”) and an optical disk drive for reading and writing to a removable nonvolatile optical disk (e.g., a Compact Disc Read Only Memory (hereinafter referred to as CD-ROM), a Digital Video Disc Read Only Memory (hereinafter referred to as DVD-ROM), or other optical media) may be provided. In these cases, each drive may be connected to the bus 18 via one or more data medium interfaces. The memory 28 may include at least one program product having a set (e.g., at least one) of program modules that are configured to perform the functions of the various embodiments of the present disclosure.

A program/utility 40 having a set (at least one) of program modules 42 may be stored, for example, in the memory 28, such program modules 42 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment. The program modules 42 generally perform the functions and/or methods of the embodiments described in the present disclosure.

The electronic device 12 may also communicate with one or more external devices 14 (e.g., keyboard, pointing device, display 24, etc.), may also communicate with one or more devices that enable a user to interact with the electronic device 12, and/or communicate with any device that enables the electronic device 12 to communicate with one or more other computing devices (e.g., network card, modem, etc.). Such communication may be performed through an input/output (I/O) interface 22. In addition, the electronic device 12 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and/or a public network, such as the Internet) through a network adapter 20. As shown, the network adapter 20 communicates with other modules of the electronic device 12 through a bus 18. It should be understood that, although not shown in the figure, other hardware and/or software modules may be used in conjunction with the electronic device 12, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

The processor 16 executes various functional applications by running programs stored in the system memory 28, such as implementing the vector instruction table filling and table lookup methods in the processor mentioned in the above embodiments.

Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

It should be noted that, in the description of the present disclosure, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present disclosure, unless otherwise specified, the meaning of "plurality" is two or more.

Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present disclosure includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present disclosure belong.

It should be understood that the various parts of the present disclosure can be implemented in hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

In addition, each functional unit in each embodiment of the present disclosure may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are illustrative and are not to be construed as limitations of the present disclosure. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present disclosure.

Claims (21)

A method for filling and looking up a table of vector instructions in a processor, comprising: A vector instruction query table is configured in a storage space preset by the processor, wherein the storage capacity of the vector instruction query table is the product of the number of items and the number of storage item bits; Determine a table filling type corresponding to the candidate vector register to be filled, wherein the table filling type includes a first type and a second type, the first type is that the product of the register width and the maximum number of register groups is greater than or equal to the storage capacity, and the second type is that the product of the register width and the maximum number of register groups is less than the storage capacity; Using a table filling rule corresponding to the table filling type, writing a first element stored in a target vector register among a plurality of candidate vector registers into the vector instruction lookup table; In a case where the table filling type is the first type, using a table filling rule corresponding to the table filling type to write a first element stored in a target vector register among multiple candidate vector registers into the vector instruction lookup table includes: Calculating a ratio of the storage capacity to a register width of the candidate vector register as a first number of registers in a register group; Determine a source register number from the numbers of the plurality of candidate vector registers; and determine a first number of registers starting from the source register number and continuing as the target vector registers; and The first element stored in the target vector register is written into the vector instruction lookup table. The method of claim 1, wherein, when the table filling type is the second type, writing the first element stored in the target vector register among the plurality of candidate vector registers into the vector instruction lookup table by using a table filling rule corresponding to the table filling type comprises: Calculating a ratio of the storage capacity to a first target value as the number of table filling times, wherein the first target value is a product of a register width of the candidate vector register and a maximum number of register groups; Determine a plurality of register groups having the same number of table filling times from the plurality of candidate vector registers, wherein each register group includes a second number of target vector registers; and The first element stored in the target vector register in each register group is sequentially written into the vector instruction lookup table. The method of claim 2, wherein determining, from the plurality of candidate vector registers, a plurality of register groups having the same number of table fills comprises: Determine, from the plurality of candidate vector register numbers, a plurality of source register numbers having the same number of table filling times, wherein the interval between the source register numbers is at least the second number; It is determined that a second number of registers starting from each of the source register numbers constitute each register group. The method of claim 3, further comprising: Determine a plurality of offset numbers corresponding to a plurality of register groups, wherein the plurality of offset numbers are integers from 0 to n in sequence, and n is a value obtained by subtracting one from the number of table filling times; Calculate the product of the offset number corresponding to each register group and a second target value as the starting fill bit of each register group in the vector instruction query table, wherein the second target value is the ratio of the first target value to the number of storage item bits; Furthermore, the step of sequentially writing the first element stored in the target vector register in each register group into the vector instruction lookup table comprises: Based on the start filling bit, the first element stored in the target vector register in each register group is sequentially written into the vector instruction lookup table. The method of claim 1, further comprising: Obtaining a second element to be queried from the vector instruction query table using a preset table query rule; and The second element is written into a preset vector destination register. The method of claim 5, wherein the obtaining the second element to be queried from the vector instruction query table using a preset table query rule comprises: Identify a vector index register; Determine the index bit width according to the number of entries in the vector instruction query table; Calculating a ratio of a register width of the vector index register to the index bit width as the number of indexes; The vector instruction query table is looked up in parallel based on the index quantity and the target index value to be queried to obtain the second element corresponding to the target index value. The method of claim 6, wherein, when the element width of the vector destination register is greater than the element width of the vector index register and the element width of the vector destination register is the same as the number of bits of the storage item, writing the second element into the preset vector destination register comprises: determining a plurality of vector destination registers; and The second element is written to the plurality of vector destination registers. The method according to claim 4, wherein The form of the table filling rule corresponding to the first type is: table_fill.v vsrc, and the form of the table filling rule corresponding to the second type is: table_fill.v vsrc,imm; wherein, table_fill.v represents the table filling for vectors in the vector instruction set, vsrc represents the source register number, and imm represents the offset number. The method according to claim 6, wherein The table lookup rule is in the form of: table_find.v vdest, vidx, where table_find.v represents a vector table lookup in the vector instruction set, vidx represents a vector index register, and vdest represents a vector destination register. A vector instruction table filling and table lookup device in a processor, comprising: A configuration module, configured to configure a vector instruction query table in a storage space preset by the processor, wherein the storage capacity of the vector instruction query table is the product of the number of items and the number of storage item bits; a determination module, configured to determine a table filling type corresponding to a candidate vector register to be filled in a table, wherein the table filling type includes a first type and a second type, the first type being that the product of the register width and the maximum number of register groups is greater than or equal to the storage capacity, and the second type being that the product of the register width and the maximum number of register groups is less than the storage capacity; a table filling module, configured to write a first element stored in a target vector register among a plurality of candidate vector registers into the vector instruction lookup table by using a table filling rule corresponding to the table filling type; When the form filling type is the first type, The form filling module is used for: Calculating a ratio of the storage capacity to a register width of the candidate vector register as a first number of registers in a register group; Determine a first number of registers from the plurality of candidate vector registers as the target vector registers; and Writing the first element stored in the target vector register into the vector instruction lookup table; The form filling module is used for: determining a source register number from the plurality of candidate vector register numbers; and A first number of registers starting from the source register number and continuing from the source register number are determined as the target vector registers. The apparatus of claim 10, wherein, when the form filling type is the second type, the form filling module is configured to: Calculating a ratio of the storage capacity to a first target value as the number of table filling times, wherein the first target value is a product of a register width of the candidate vector register and a maximum number of register groups; Determine a plurality of register groups having the same number of table filling times from the plurality of candidate vector registers, wherein each register group includes a second number of target vector registers; and The first element stored in the target vector register in each register group is sequentially written into the vector instruction lookup table. The apparatus according to claim 11, wherein the form filling module is used to: Determine, from the plurality of candidate vector register numbers, a plurality of source register numbers having the same number of table filling times, wherein the interval between the source register numbers is at least the second number; It is determined that a second number of registers starting from each of the source register numbers constitute each register group. The apparatus of claim 12, further comprising: A first calculation module is used to determine a plurality of offset numbers corresponding to a plurality of register groups, wherein the plurality of offset numbers are integers from 0 to n in sequence, and n is a value obtained by subtracting one from the number of table filling times; A second calculation module is used to calculate the product of the offset number corresponding to each register group and a second target value as the starting fill bit of each register group in the vector instruction query table, wherein the second target value is the ratio of the first target value to the number of storage item bits; Furthermore, the table filling module is used to: based on the start filling bit, write the first element stored in the target vector register in each register group into the vector instruction lookup table in sequence. The apparatus of claim 10, further comprising: The table lookup module is used to obtain the second element to be queried from the vector instruction lookup table using a preset table lookup rule; and write the second element into a preset vector destination register. The apparatus of claim 14, wherein the table lookup module is used to: Identify a vector index register; Determine the index bit width according to the number of entries in the vector instruction query table; Calculating a ratio of a register width of the vector index register to the index bit width as the number of indexes; The vector instruction query table is looked up in parallel based on the index quantity and the target index value to be queried to obtain the second element corresponding to the target index value. The apparatus of claim 15, wherein, when the element width of the vector destination register is greater than the element width of the vector index register, and the element width of the vector destination register is the same as the number of bits of the storage item, the table lookup module is configured to: determining a plurality of vector destination registers; and The second element is written to the plurality of vector destination registers. The device as claimed in claim 13, wherein The form of the table filling rule corresponding to the first type is: table_fill.v vsrc, and the form of the table filling rule corresponding to the second type is: table_fill.v vsrc,imm; wherein table_fill.v represents the table filling for vectors in the vector instruction set, vsrc represents the source register number, and imm represents the offset number. The device of claim 15, wherein The table lookup rule is in the form of: table_find.v vdest, vidx, where table_find.v represents a vector table lookup in the vector instruction set, vidx represents a vector index register, and vdest represents a vector destination register. An electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 9. A non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause the computer to execute the method according to any one of claims 1-9. A computer program product comprises a computer program, wherein when the computer program is executed by a processor, the method according to any one of claims 1 to 9 is implemented.