KR20050099967A - Memory interleaving - Google Patents

Abstract

Memory interleaving includes providing a non-square number of channels in a computing system and interleaving memory access among the channels.

Description

Methods, articles of manufacture, digital devices and systems {MEMORY INTERLEAVING}

The present invention relates to memory interleaving.

Channels are generally referred to as paths between computer systems and other computer systems and / or other devices. Each of the channels of the computing system is an independent unit capable of transmitting data simultaneously with other channels. Each channel is typically assigned to a segment of a memory address space and can carry data corresponding to that allocated memory address space. In this manner, a processor of a computing system may access different segments of memory through different channels without idling while the memory completes access to one segment before initiating another memory access. This type of memory access is generally referred to as interleaving.

1 is a block diagram of an example of a channel control system.

2 is a flowchart of an example of a memory interleaving process.

3 is an example flowchart of a process for determining whether a given area is present in a channel.

4 is a flowchart of an example of an address reduction process.

5 is a block diagram of an example of address reduction.

6 is a block diagram of one example of an address adjustment process.

7 is a flowchart of an example of an address remapping process.

8 is a block diagram of an example of a machine system.

Referring to FIG. 1, an example channel control system 100 may interleave access to memory using channel controllers 102 (1)-102 (x), each associated with one channel. x is any positive integer greater than 1, and includes non-square positive numbers (3, 5, 6, etc.). Whatever the value of x, interleaving can be performed without using one or more bits of the memory address indicating which channel to use for memory access. Since the address bits need not be used in channel selection, the number of channels for interleaving is not limited to the number of squares of channels as in conventional channel interleaving. The address may be mapped to channel controllers 102 (1) -102 (x), and access to the memory may be done simultaneously for addresses mapped for different channels.

Each of the channel controllers 102 (1) -102 (x) has one of x match detection mechanisms 104 (1) -104 (x) and x address and count remapping mechanisms 106 (1) -106. (x)). Each channel controller 102 (1) -102 (x) receives information about a given area to access in memory, and determines whether the associated channel is mapped to access data contained in that area. do. Channel controllers 102 (1) -102 (x) typically make decisions in parallel, but the controller can process the information according to some pre-programmed priority or ordering scheme.

The information received by the channel controllers 102 (1) -102 (x) includes a start address indicating where to start accessing data in the memory and a count indicating how much data to initiate access at the start address. It may include a data pair. The count is typically provided in bytes, but any data measurement or size indicator may be used. The start address and count define a predetermined area starting at the start address and extending for the number of bytes indicated by the count (or otherwise indicated by the count depending on how the count is provided).

Each of the match detection mechanisms 104 (1) -104 (x) determines whether the associated channel is mapped to any of the addresses included within that region. Addresses are mapped to channels using a conventional scheme of allocating address space segments for a channel, or using a scheme described below so that adjacent addresses can be spread over multiple channels by spreading adjacent addresses over the channels. The channel may be mapped to access no address included in the area, all addresses included in the area, or some address included in the area. If a channel is mapped to some address included in that region, that portion of the region is within that channel and at least two channels are mapped to that region and all can access the region.

If one of the match detection mechanisms 104 (1) -104 (x) determines that a portion of that region exists within its associated channel, then the address and count remapping mechanism associated with that channel 106 (1) -106 (x) One determines the remapped start address and the remapped count indicating the portion of access that the related one of the channel controllers 102 (1) -102 (x) completes. Although the address and count remapping mechanisms 106 (1) -106 (x) can determine the remapped address and the remapped count, the match detection mechanism 104 (1) -104 (x) is an area to store in processing. Determine if the channel will be mapped.

Once the channel controllers 102 (1) -102 (x) have determined that their associated channels have mapped to that area, the appropriate one of those channels can access the data in the indicated area. In this way, an address can be mapped to channels so that multiple channels can be used to access data at a relatively close address. In addition, the interleaving scheme may include using two or more channels including a non-square number of channels.

In another example, match detection mechanisms 104 (1) -104 (x) and / or address and count remapping mechanisms 106 (1) -106 (x) are channel controllers 102 (1) -102 (x). May be external to). In addition, some or all of the channel controllers 102 (1) -102 (x) may have the same match detection mechanism 104 (1) -104 (x) and address and count remapping mechanisms 106 (1) -106 ( x)) can be used.

2 shows a process 200 of memory interleaving. In process 200, channel controller 102 receives (202) address and count information about an area to access in memory. Each channel controller 102 (1) -102 (x) receives the same information.

Each of the channel controllers 102 (1) -102 (x), match detection mechanisms 104 (1) -104 (x) and address and count remapping mechanisms 106 (1) -106 (x) each correspond to similarly named names. Functions similarly to a negative part, for simplicity, the match detection mechanism 104 (1) ("match detection 104") included in the channel controller 102 (1) ("channel controller 102") and The address and count remapping mechanism 106 (1) ("remapping 106") is used as a representative example.

The match detection mechanism 104 determines how many regions are present in the channel associated with the channel controller 102, in this embodiment channel 1. Examples of how match detection mechanism 104 makes such a determination are discussed in more detail below.

If no area exists in the channel, process 200 ends (206) because the data to be accessed cannot be accessed through the channel.

If the region is entirely within the channel, then channel controller 102 triggers an access of the amount of data equal to the count starting at the start address over that channel (208). Channel controller 102 may retrieve the data by itself.

If a portion of that region is present in the channel, the remapping mechanism 106 adjusts the address and count to the adjusted address and adjusted count such that the channel only accesses data in the allocated region. Channel controller 102 can trigger an access of a data amount equal to the adjusted count that is initiated at the adjusted start address over the channel (212). Channel controller 102 may retrieve the data by itself. For example, the start address may be indexed within one channel, but the count may extend to an area within the area that is mapped to another channel, and the other channel where the area starts within the indexed area. You need to adjust the start address to reflect this. The adjusted start address may be the same as the start address, but the adjusted count is different from the count when the count extends beyond the mapped region of the channel.

3 shows an example of decision processing 300 where match detection mechanism 104 is present in a channel and whether there is a certain amount of area. In decision processing 300, match detection mechanism 104 calculates (302) the upper address of the region corresponding to the endpoint of the data contained within that region. The match detection mechanism 104 may calculate the upper address as the start address plus the count minus 1. 1 is subtracted to describe the data at the start address.

The match detection mechanism 104 reduces 304 the upper address and the start address to two bits, respectively. Due to each address reduced to two bits, match detection mechanism 104 may determine whether the region is at least partially within a channel associated with the match detection mechanism. The addresses can be reduced to two bits each, because in this embodiment including three channels (x corresponds to three), a combination of two bits where each channel is different (eg, "01 for channel 1"). &Quot;, " 10 " for channel 2, " 11 " for channel 3, wherein the representation of the two bits of the channel containing the address is reduced in address and associated with match detection mechanism 104. It can be used to help determine if a channel is mapped to the region. If the system includes more than two channels, the address can be reduced to more than two bits, because two or more bits may be needed to represent each of the different channels. Examples of how match detection mechanism 104 performs the reduction will be discussed in more detail below.

The match detection mechanism 104 determines 306 whether the channel number associated with the match detection mechanism 104 matches the reduced high address or the reduced start address. If not, there is no region within that channel.

If the reduced address matches the channel number, match detection mechanism 104 determines whether both the reduced high address and the reduced start address match the channel number (308). If so, the whole area is within the channel. If not, only one of the reduced addresses matches the channel number, and only part of that area will be present in the channel. The match detection mechanism 104 determines 310 whether the reduced start address matches the channel number. If so, the lower part of the data transfer (access), starting at the start address, will be in that channel. If not, the match detection mechanism 104 is initiated at an upper portion of the data transfer, an address higher than the start address and continuing through the upper address (if the start portion of the upper portion is not an upper address and in that case the data is It is concluded that the upper part of the transfer is in the channel only if it contains only the upper address. In this embodiment, the match detection mechanism 104 checks the match with the start address and makes assumptions about higher address matching based on the determination, but in another example the match detection mechanism 104 checks the high address and Make assumptions about the start address.

4 shows an example of reduction processing 400 that the match detection mechanism 104 can use to reduce the address. As shown in the address reduction 500 of FIG. 5, in the reduction processing 400, the match detection mechanism 104 reduces the 31-bit address 502 to the 21-bit output number 504 for five levels of gating. Take The match detection mechanism 104 may ignore one or more bits contained in the address 502 that are not part of the start or higher address. In this embodiment showing the start address, the match detection mechanism 104 considers the start address of 24 bits while ignoring the seven bits contained in the address representing the byte offset. One of the gating levels takes the channel number 506 of the channel holding the address as input.

Referring back to FIG. 4, the match detection mechanism 104 records (402) the address using two to two bit recording to include the same bits (24 bits) as the addresses according to the table below. Generates one number of bits.

The match detection mechanism 104 records (404) the first number of bits using a 4-bit to 2-bit reducer, reducing the number of half of the first number of bits (24 bits) according to the table below. Second number of bits).

The match detection mechanism 104 reduces (406) a second number of bits according to the four-bit to two-bit reducer table to include one half of the second number of bits (12 bits are reduced to 6 bits). Generates 3 bits.

The match detection mechanism 104 reduces (408) the fourth number of bits (8 bits reduced to 4 bits) by reducing the third number of bits plus channel number including the address according to the 4-bit to 2-bit reducer table. Create If the match detection mechanism 104 did not include the channel number as an input in this reduction then there would be two unused inputs. The match detection mechanism 104 receives the channel number from the remapping 106 and may refer to it in an address mapping table that indexes the address and its corresponding channel number, or otherwise obtain the channel number.

The match detection mechanism 104 adds 410 the last two 2-bit recorded numbers. The sum of zero, 1 and the two is unchanged, but the four sums are zero. This summation will result in a final 2-bit output reduction.

The match detection mechanism 104 determines whether the final output represents a match with the channel associated with the match detection mechanism 104 (412). The final output of zero (00) indicates a match, but 1 (01) or 2 (10) indicates a mismatch. Including the channel number associated with the address (start address or higher address) as an input in the reduction processing allows the match detection mechanism 104 to make a match decision from the last bit output of the reduction processing.

6 illustrates an example of coordination processing that remapping 106 may use to adjust the start address and count if the match detection mechanism 104 determines that only a portion of the region is present in its associated channel (see FIG. 2). 600).

In coordination processing 600, remapping 106 calculates a boundary address that represents an address that is an interleaved amount that exceeds the start address (602). The interleaved amount is typically contained within an address that includes a start address (eg, address 502 of FIG. 5), which is equal to 128 bytes in this embodiment. Remapping 106 may calculate the boundary address by performing a logical AND operation on the start address and 0xFFFFFF80 to add 0x80 (interleaved amount).

Remapping 106 also calculates a low count that indicates the number of bytes between the start address and the boundary address (604). The remapping 106 can calculate the lower count by subtracting the start address from the boundary address.

Remapping 106 also calculates a high count that indicates the number of bytes between the boundary address and the stop address (start address plus count) (606). Remapping 106 may calculate the upper count by subtracting the boundary address from the stop address and adding 1 (1 describes the fact that the lower count includes the boundary address).

If the channel associated with the remapping 106 owns a lower portion of the transfer (eg, as determined via decision processing 300), the remapping 106 will convert the adjusted start address to the start address and the adjusted count. Is considered as the lower count (608). If not (ie, if the channel associated with remapping 106 owns the upper portion of the transfer), remapping 106 considers the adjusted start address to the boundary address and the adjusted count to the upper count. 610.

7 shows an example of remapping processing 700 that remapping 106 may use to index addresses in a channel. Remapping 106 finds 702 the longest length string of consecutive address bits with one value in the address to be indexed. Remapping 106 begins searching for the longest string with the least significant bit in the address. Once found, remapping 106 drops the longest string from that address (704) and justifies the remaining bits in that address (706). If the channel contains a number of squares of memory locations (eg, addresses), remapping 106 fills the empty bit positions (most significant bits) with 1 (708). This filling essentially adds three quarters to the space of the remaining channel. That is, it starts to fill three quarters from the address. The last bit forms a remapped address.

If the channel consists of a non-square number, the shifting of 3/4 will typically not have the same size as the number of channels of the square (e.g. it will be a number other than a two bit position). Remapping 106 determines where to add 1 in the empty position (710). Remapping 106 may make the foregoing decision by consulting one or more lookup tables that include a constant indicating a start address that begins filling 1 (712). Each lookup table is contained within remapping 106 or otherwise accessible to remapping 106 and may include constants for any number of channels and any number of shifted bits. The final bits form a remapped address.

For example, in a three-channel system, the lookup table is as follows, where the constant value is shown in hexadecimal, KO represents three quarters of one channel, K1 represents three quarters plus three quarters of one channel. , K2 represents 3/4 plus 3/4 plus 3/4 of one channel. The lookup table represents constant values up to 768 MBytes, but the values in the lookup table can be scaled to one that is suitable for a large number of MBtye.

Remapping 106 indexes all available addresses, such as all addresses processed by channel control system 100 (see FIG. 1). As a simple example, in a system that includes three channels with eight addresses and twenty-four addresses, the address locations within the channels would be remapped as shown.

Although the processing of FIGS. 2, 3, 4, 6, and 7 has been described with reference to components included within the channel control system of FIG. 1, the above or similar processing including the same, more, or fewer components. These may be performed in the channel control system 100 or other similar system. Also, while the processing of Figures 2, 3, 4, 6, and 7 has been described as a system using 128 byte interleaving, including three channels and 31 bit addresses, these processing may be any size of interleaving, any number of Can be used (via any suitable modification) for channels and addresses of any size. In addition, the processing in FIGS. 2, 3, 4, 6 and 7 need not be performed in all of the systems, but may find applicability either alone or in partial combination with two or more other processing.

Referring to FIG. 8, machine 800 includes a processing system 802 that includes a memory controller 804 that may include or similarly be configured for a channel control system 100. Components described with reference to FIG. 8 may be implemented in various ways.

The consuming device 806 may need information stored at a predetermined location in the main memory 808. The consuming device 806 typically connects to the machine 800 through input / output (I / O) ports, bays, and slots 810 to provide the chipset 812 and processor (from the main memory 808). 814 request data.

Memory controller 804 may control access to the mapping address in main memory 808 as described above while interleaving reads / writes using multiple memory channels. Main memory 808 may include any memory mechanism capable of storing data. Examples of main memory 808 include random access memory (RAM), such as dynamic RAM or static RAM, ROM, flash memory, tape, disk, buffer, and other types of similar storage mechanisms. Main memory 808 may include one storage mechanism, such as one RAM chip or any combination of storage mechanisms, such as multiple RAM chips. For example, the memory may comprise SDRAM. SDRAM generally refers to a type of DRAM that can operate at a faster clock speed than conventional memory. The SDRAM may itself synchronize with a bus associated with a processor (eg, processor 814) included in the computing system. DDR-SDRAM generally refers to a type of SDRAM that supports data transfer on all edges of each clock cycle, effectively doubling the data throughput of the memory.

Machine 800 may include any mechanism or device capable of processing data. Examples of machine 800 include workstations, stationary personal computers, mobile personal computers, servers, PDAs, pagers, telephones, and other similar mechanisms and devices.

The consuming device 806 may include an I / O device, a network interface, or other mechanism that may be in communication with or included in the machine 800. I / O devices generally include devices used to convey data to a computer system. Examples of I / O devices include display devices such as mice, keyboards, printers, monitors, disk drives, graphics devices, joysticks, paddles, zip drives, scanners, CD drives, DVD drives, modems, cameras , Video devices, microphones, and other similar types of internal, external, and internal / external devices. Although one consuming device is shown, the machine 800 can communicate with more consuming devices.

I / O ports, bays, and slots 810 may include any mechanism or interface that may connect one or more consumer devices to the machine 800. For example, I / O ports, bays, and slots 810 may include peripheral component interconnect (PCI) slots, parallel ports, serial bus ports, disk drive bays, and other similar types of mechanisms and interfaces.

Processor 814 may include any processing mechanism, such as a microprocessor or central processing unit (CPU). Processor 814 may include one or more individual processors. Processor 814 may include a network processor, a general purpose embedded processor, or another similar type of processor.

Chipset 812 may include any number of chipset / integrated circuitry that may provide an interface between subsystems of a machine.

Instructions and data are typically communicated in blocks to main memory 808. A block generally refers to a collection of bits or bytes that are communicated or processed as a group. A block can contain any number of words, and a word can contain any number of bits or bytes.

Data can be communicated between components on the communication link. The communication link may include any kind of communication link and combinations thereof, such as buses (of any type and size), physical ports, wireless links, and other similar links. For a bus communication link, the bus can have any width, such as 16 bits, 32 bits, 64 bits, and the like, and can operate at any speed, such as 33 megahertz (MHz), 100 MHz, and the like. The bus may have sideband characteristics, where the bus includes parallel channels capable of carrying data and address information simultaneously. In addition, each communication link may comprise one or more individual communication links.

The memory controller 804 is generally in communication with the main memory 808 and includes any mechanism capable of managing this memory. The memory controller 804 may include one or more chipsets and may be included in the chipset 812 or may be a mechanism independent of the chipset 812. The memory controller 804 may include any number of any type of instructions, routines, applications, and programs.

In addition, the machine 800 is simplified to facilitate description. Machine 800 may include additional components such as communication links, processors, storage mechanisms (buffers, caches, memory, databases, etc.), display mechanisms, consumer devices, bridges, chips, and other similar types of machine elements. .

The techniques described herein are not limited to any particular hardware or software configuration, and these techniques can be applied to any computing or processing environment. These techniques can be implemented in hardware, software, or a combination thereof. These techniques include mobile computers, fixed computers, PDAs, and processors, storage media readable by the processor, the storage media including volatile and nonvolatile memory and storage elements, at least one input device, and one or more outputs. It may be implemented as a program running on a programmable machine, such as a similar device including a device. The program code is applied to data input using the input device to perform the described function to generate output information. Output information is applied to one or more output devices.

Each program can be implemented in a high level procedural or object oriented programming language to communicate with a machine system. However, this program can be implemented in assembly or machine language, if desired. In any case, the language can be a compiled or interpreted language.

Each such program may be stored on a storage medium or device, such as a CD-ROM, hard disk, magnetic disk, or similar medium or device, wherein the storage medium or device is read by a computer to perform the procedures described herein. It is readable by a general purpose or special purpose programmable machine for configuring and operating the machine as it is intended to be performed. The system is also considered to be implemented as a machine readable storage medium consisting of programs, wherein the storage medium is configured for the machine to operate in a particular prescribed manner.

Other embodiments are within the scope of the appended claims.

Claims (33)

Providing a non-square number of channels in the computing system, Interleaving a memory access between the channels; Way. The method of claim 1, Enabling interleaving without using any address information indicating which channel to use for memory access. The method of claim 1, Assigning a group of memory addresses for each channel, Enabling interleaving by simultaneously accessing memory addresses in different groups using different channels. The method of claim 1, Providing three channels. Receiving a request for access to a memory of a memory area included in the memory; Determining whether one of the non-square numbers of memory channels is mapped to at least a portion of the memory area; If so, using the determined memory channel to access a portion of the memory region mapped to the determined memory channel. Way. The method of claim 5, Receive a memory access through the request, Reduce the memory address to 2 bits, Taking the channel number of the memory channel into consideration when reducing the memory address to 2 bits, By determining if the memory channel is mapped for at least a portion of the memory area if the two bits match the channel number. Determining whether a memory channel is mapped for at least a portion of the memory area. The method of claim 6, Receive the amount of data to access a memory address via the request, Calculate an upper address corresponding to the address above the memory address by the amount of data, Determine if two bits match the channel number but not the number corresponding to the higher address, and if so, determine that the channel is mapped to the portion of the memory area starting at that memory address and And determine whether the two bits match the number but not the channel number, and if so the channel maps to a portion of the memory area starting at the boundary address that is an interleaved amount exceeding the memory address. Decided to be, and By accessing only the amount of data contained within the portion of the memory area using the determined channel. Determining whether the memory channel is mapped to a portion that includes less than all memory regions. The method of claim 7, wherein If a memory channel is mapped to a portion that contains less than all memory regions, Calculate a first count as the boundary address minus the memory address, A second count is calculated as an address that is a data amount exceeding the memory address minus the boundary address, Access the memory region for the first count starting at the memory address if the channel is mapped to a lower portion of the memory region, and By accessing a memory region for the second count starting at the boundary address if the channel is mapped to an upper portion of the memory region, Determining a method of accessing the amount of data contained in the portion of the memory area. The method of claim 5, Receiving the amount of data to be accessed at the memory address via the request; Accessing the amount of data at the memory address using the determined channel. An article of manufacture comprising a machine accessible medium for storing an executable instruction, the article of manufacture comprising: The instruction causes the machine to Receiving a request for access to a memory of a memory area included in the memory; Determining whether one of the non-square numbers of memory channels is mapped to at least a portion of the memory area; If so, use the determined memory channel to access a portion of the memory region mapped to the determined memory channel. Manufactured goods. The method of claim 10, Let the machine An article of manufacture that enables interleaving without using any address bits that indicate which channel to use for memory access. The method of claim 10, Let the machine Assign a group of memory addresses to each channel, An article of manufacture that enables interleaving by simultaneously accessing memory addresses in different groups using different channels. Determine a longest string of consecutive bits with a value of 1 in the address, Drop the longest string from the address, Justifies the remaining bits in the address, By filling the empty bits in the address with 1 to generate a remapped address that is indexed for one of the memory channels, And mapping an address for one of the plurality of memory channels. The method of claim 13, Providing a non-square number of memory channels. The method of claim 13, Distributing an equal number of remapped addresses for each memory channel. The method of claim 13, The address comprises a main memory address. The method of claim 13, Wherein the address comprises any address that can be mapped to a machine source. The method of claim 13, Filling the empty bits starting at a start address equal to the address plus a predetermined constant value. The method of claim 18, Providing a constant value of three quarters if there is a square number of memory channels. The method of claim 18, If there is a non-square number of memory channels, further comprising consulting a table containing constant values for different numbers of memory channels to determine the constant value. An article of manufacture comprising a machine accessible medium for storing an executable instruction, the article of manufacture comprising: The instruction causes the machine to Determine a longest string of consecutive bits with a value of 1 in the address, Drop the longest string from the address, Justifies the remaining bits in the address, By filling the empty bits in the address with 1 to generate a remapped address that is indexed for one of the memory channels, To map an address to one of a number of memory channels Manufactured goods. The method of claim 21, And causing the machine to distribute the same number of remapped addresses for each memory channel. The method of claim 21, Wherein the address comprises a main memory address. The method of claim 21, Wherein the address comprises any address that can be mapped to a machine source. The method of claim 21, And causing a machine to fill the empty bits starting at the same start address as the address plus constant value. The method of claim 21, And causing the machine to provide a constant value of three quarters if there are a square number of memory channels present. The method of claim 21, And causing the machine to determine a constant value by consulting a table that includes the constant value for a different number of memory channels if there is a non-square number of memory channels. As a digital device, A processor capable of executing instructions, Let the processor: Allow one of the non-square numbers of memory channels to be mapped to at least a portion of the main memory area that received the request for access, and If so, the memory includes instructions for using the determined memory channel to store instructions for accessing a portion of the mapped memory region for the determined memory channel. Digital devices. The method of claim 28, And a chipset accessible by the processor and including a memory for storing instructions. The method of claim 28, The memory for storing instructions causes the processor to Assign a memory address group in main memory for each memory channel, and A digital device capable of simultaneously accessing memory addresses in different groups using different memory channels. A non-square number of memory channels for accessing the memory, And to map an address contained in the memory to the memory channel, and to determine whether one of a non-square number of memory channels is mapped to at least a portion of a memory region starting at an address contained in the memory. And if so, including a memory controller configured to access the portion of the memory region mapped for the determined memory channel using the determined memory channel. system. The method of claim 31, wherein The memory controller is also Determine a string of the longest length of consecutive bits having a value of 1 in the address, Drop the longest string from the address, Justifies the remaining bits in the address, By filling the empty bits in the address with 1 to generate a remapped address that is indexed for one of the memory channels, And map an address contained within the memory to the memory channels. The method of claim 31, wherein The memory controller is also configured to enable simultaneous access of regions of the memory using different memory channels.