JPS58208982A - Store buffer - Google Patents

Abstract

PURPOSE:To improve the effect of write degeneration of a store buffer, by suppressing the write to the store buffer in response to a count time where the number of write accesses in the store buffer and the write access are stored. CONSTITUTION:A registration pointer 25 of a store buffer 12 and a readout pointer 33 are compared and whether or not the number of write requests stored in an associative memory 15 reaches a prescribed number is detected at a word detecting circuit 41. On the other hand, a prescribed number is set to a store suppressing counter 42 counting (-1) at each machine cycle, every time a write request from an instruction executing section 11 is given so long as the count value is not zero, and the time storing the write access is counted. When the number of detection of the circuit 41 reaches a prescribed number or over and the count value of the counter 42 is zero, the suppression of the write request with the store buffer control circuit 43 is released. Then, the write to the store buffer is controlled suitably, by write degeneration effect of the store buffer is improved and the competition of data in the store buffer of the like is preveted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the present invention pertains] The present invention relates to a store buffer in a 1/6 information processing device.

[Summary of Prior Art] In information processing devices that require high-speed processing, high-speed, small-capacity graphics memory is generally installed in order to reduce the difference in processing time between the central processing unit and the main memory. .

As a buffer memory method.

The store-through method, in which data is written to both the buffer memory and the main memory when writing data, is often adopted because of its ease of implementation. In a device in which there is a large difference in processing time between the central processing unit and the main memory, it is necessary to reduce the number of accesses to the main memory in order to reduce performance degradation due to processing competition in the main memory. For this purpose, the buffer memory capacity is increased, but in a store-through type buffer memory, even if it is effective for data reading, the main storage is always used for data 1. , the number of write accesses cannot be reduced. Furthermore, the processing speed of the main memory device cannot keep up with multiple write requests from the central processing unit that are close in time, which causes a decrease in performance. A store buffer is one of the means to solve these problems.

The store buffer is mainly composed of an associative memory circuit in which a write address to the main memory is stored and whose stored contents can be indexed, and a data buffer circuit that stores write data corresponding to the content addressable memory circuit. Both circuits are generally constructed of multiple words and can store write information to multiple different addresses. Writing to main memory is performed via a store buffer.

One of the purposes of the store server is to smooth write requests on the time axis. When multiple write requests are made from the central processing unit at time intervals faster than the processing speed of the main storage device,
± addresses and write data are stored in the store buffer. When the central processing unit registers with the store buffer, it considers that the write process has ended and can proceed to the next process, so continuous write requests are not made until the store buffer is full. It becomes possible to continue the processing of the central processing unit without being affected by the processing speed of the main storage device.

Another purpose of the store buffer is to reduce the number of accesses to main memory by degenerating write requests.

When registering a write request to the store buffer, the content addressable memory circuit is indexed using the write address, and if a write to the same address has already been registered, one new word of the store buffer is used. The write data is overwritten on the word of the data buffer circuit corresponding to the word in which the same address is registered.

When the data width to main memory is 8 bytes.

One word of the data buffer circuit is prepared with 8 or more bytes, but on the other hand, the number of write requests generated by the central processing unit is 4.
It is often less than a byte, and writing to nearby addresses is high. The above-mentioned overwriting can be expected when writing to the same address or writing to an adjacent address, but this overwriting (degeneracy of code) can reduce the number of write accesses to the main memory. .

For example, in a 4-byte wide store with continuous addresses, which is often seen in FORTRAN single-precision floating point or fixed point array operations, if there is no degeneracy function, a 1 [1] store access will result in a 4-byte store.

If the degeneracy function works ideally, two 4-byte stores can be converted into one 8-byte store, and when the data width with the main memory is 8 bytes, the number of stores can be halved. . Especially in main memory which is interleaved with 8-byte width.

Without the degeneration function, a 4-byte partial byte write request to the same puncture would be made twice, but when the degeneration function is activated, successive stores will result in full byte write requests to different punctures in the main memory. This is done as an efficient main memory access.

Generally, the processing cycle of a main memory device is faster for a full byte write request than for a partial byte write request.

[Disadvantages of conventional technology]

By the way, in a conventional store buffer, if the 7th ace connected to the main memory is empty, the first storage buffer is
・Main 611 from store buffer on first out. t
No. 5 is inserted into the device. For this reason, main note 1 (5)
Even if store accesses to the same 78 bytes are made in close proximity when the interface with the device is empty, the store access that was accessed earlier will be transferred from the store buffer to the main memory by the time the subsequent store access reaches the store buffer. Since the device is accessed, degeneration cannot be performed.

Store access must be made again to the same interface in the main memory. In a multi-processor system where the main memory is shared between processing units, it is necessary to reduce the number of accesses to the main memory from each processing unit as much as possible in order to reduce contention for main memory access between processing units. For this reason, it is necessary to increase the number of degenerate fruits, but in conventional store buffers, the opportunity for degeneracy is often missed, causing a decrease in the processing speed of /stem.

[Object of the present invention]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a store buffer as described above, which improves the degeneracy effect of writing and further reduces the number of accesses to the main storage device.

[Summary of the invention]

In order to achieve the above object in the present invention.

The store buffer is provided with a function of holding valid write information of 111 or more at a certain time, thereby minimizing the deterioration of the degeneracy function and preventing the deterioration of the function due to contention in the main storage device as much as possible.

That is, according to the present invention, write data accompanying a write access from a processing device to a recording device is held in a degenerate manner,
In a store buffer having a function of controllably issuing a write request to write the held data to the storage device, a number of words detecting means for detecting the number of write accesses in the store buffer; and a timer for counting the time during which a 1-input access is held in the store buffer, and the means for controlling the write request calculates the number of write accesses detected by the Ms password detection means. is within a predetermined number and the time counted by the timer has not reached the predetermined value,
A store buffer characterized in that it also has a function of suppressing the write request is obtained.

[Details of conventional technology]

First, a conventional store buffer will be explained in detail in order to clarify the features of the present invention. Since this conventional device is almost completely included in the device according to the present invention, the following description will be used almost as is as the first half of the description of one embodiment of the present invention.

Figure 1 is a block diagram showing the configuration of a conventional store buffer along with devices necessary for its control. In FIG. 1, 11 is an instruction execution unit, 12 is a store buffer to which the present invention is applied, and 13 is a main storage device. storeba,
7712 includes a store buffer control circuit 14, an associative memory circuit 15 that holds a write address and can index the held address, and a write data buffer circuit 16 that holds write data corresponding to this address. , hold the bit indicating the validity of this write data in correspondence with the byte of the write data/(ite specification/guffa 17,
It is composed of a large number of peripheral circuits (described in sequence later).

When the instruction execution unit 11 requests a write to the store buffer 12, a write request signal a, a write address b, write data C, and a byte designation d are sent.

a storer/fa control circuit 14, an input address renostar 21, and an input write data renostar 22.

Each is sent to the input byte designation register 23.

The byte designation d is larger than 8 bits when the write data is 8 bits, and each bit specifies the bit to be written in comparison with each bit of the write data. In the input address reno star 21, the associative memory 15 is stored at that address.
index. That is, it is checked whether an address that matches the address e from the input address register 21 and whose valid bit 24 is 1'' is held in the associative memory 15.

If there is no match as a result of the index in the associative memory 15, the store buffer control circuit 14 sets the registration pointer 25 to
The address of the input address reno star 21 is registered in the word of the associative memory 15 indicated by , and the valid bit 24 is set to 1''.
be made into At this time, the contents of the registration pointer 25 are sent to the write data buffer 16 and the byte designation buffer 17 through the registration word selection circuit 26, and the contents of the input write data register 22 and the input and byte designation register 23 are sent to the corresponding words. The contents of are registered.

At the same time, the contents of the registration pointer 25 are incremented by 1 by the registration counter 27.

If a matching word is found as a result of the index in the content addressable memory circuit 15, a write degeneracy operation is performed.

At this time, the contents of the associative memory 15 are not changed.

The word number f that matches in the associative memory circuit 15 is sent to the byte designation buffer 17 through the read word selection circuit 28 and the registered word selection circuit 26.

Then, the content of the input write data register 22 is bit 1, which is "1" of the noster 23 that specifies the input pie.
Only the Might corresponding to is written to the word specified by the output of the registered word selection circuit 26 of the write data buffer 16. The byte that specifies the input byte and corresponds to the 0" (pi) of the nostar 23 is not changed.

The byte specification creation circuit 29 specifies the input byte and outputs the soster 2.
The bit-by-bit OR of the data No. 3 and the data read from the byte designation software 17 is calculated.

This output becomes information to be written to the byte designation buffer 17. Writing is performed to the word specified by the registered word selection circuit 26. With this operation, two writes to the same address are reduced to one write on the store buffer 12.

Next, a write process from the store buffer 12 to the main storage device 13 will be explained. When there is no valid write request in the input address reno star 21.

Or, even if there is a mismatch in the associative memory circuit 15, the content of the word designated by the read pointer 25 is read from the associative memory circuit 15, write data buffer circuit 16, and byte designation buffer 17. If the valid bit 24 of this word is 1'' and the output address register 30 is empty, the respective contents are sent to the output address renoster 30° output write data renoster 31 and output byte designation register 32. At the same time, the valid bit 24 corresponding to the word is set to 0'', and the contents of the read pointer 33 are incremented by 1 by the read counter 34.

As described above, valid write request information is transmitted to the output address register 30. When set in the output write data reno star 31 and output byte designation register 32, the main memory 1
3, if the interface is free, a write request g is made.

A write address h, write data l, and byte designation j are each sent. When the interface with the main storage device 13 is not empty, waiting is performed. In this way, if the interface of the main storage device 13 is empty, a write request e is immediately issued to the main storage device, so as mentioned earlier,
Even if a write request is subsequently made to the store buffer 12 at the same address, the degeneracy operation cannot be performed because the previous write request no longer exists in the store buffer.

The contents of the read pointer 33 and the contents of the registration pointer 25 are initially set equal. The read pointer 33 indicates a word to issue a write request to the main memory 13, and the registration pointer 25 indicates a word to register a write request from the instruction execution unit 11. The value obtained by subtracting the read point value from the registered point value indicates the number of valid write requests existing in the associative memory 15.

When the registered point value and the read point value are equal and the corresponding valid bit 24 is "1", it indicates that the associative memory 15 is full. When the associative memory circuit 15 becomes full, there is a valid write request to the input address renoster 21, and there is no matching word 1 in the index result of the associative memory circuit 15, the associative memory circuit 15 becomes empty. The registration processing 17 waits for one row until the occurrence of the registration process.

Indexing of the associative memory circuit 15 is also performed when a read request to the main memory 13 is made. This is done because when reading from the same address occurs after writing to a previous address, it is necessary to read the data after the previous writing. When a word with a matching address is detected as a result of the index, the store buffer 12
A read request is suppressed until a match is no longer detected in the associative memory circuit 15 due to a write request to the main memory device 13 .

[One embodiment of the present invention]

Figure 2 shows the configuration of one embodiment of the present invention in block form.
・This is the diagram shown. In Figure 2, reference numerals 11-1
The ranges shown by 3 and 15 to 34 correspond to the conventional device shown in FIG.
is particularly added in the present invention.

Also, the function of the store buffer control circuit has changed, and 43 is given instead of 14. The word count detection circuit 41 compares the contents of the registration pointer 25 and the read pointer 33,
It is detected whether the number of write requests currently stored in the associative memory 15 is a predetermined number of M words. For example, when the result of adding 1 to the bit-by-bit inversion of the contents of the read pointer 33 and the contents of the write pointer 25 is M, it means that the write request is held with an M fine needle.

The store inhibition counter 42 is set to a predetermined value N when the write request signal a is sent from the instruction execution unit 11. N varies depending on the device, but is approximately 9, for example, 10. Thereafter, the content is counted by 11 every machine cycle, and when it reaches 0, the -1 counting operation is stopped. When the write request signal a is further sent before reaching 0,
The value N is set again and the same operation is repeated.

In the store buffer control circuit 43, the word number detection circuit 4
When 1 indicates that the number of write requests currently stored and viewed is M words and the value of the store inhibition counter 42 is not O, the transmission of write requests to the output address register 30 etc. is inhibited. do. When the above conditions are not satisfied, the same operation as a conventional store buffer is performed.

Due to the above operation, when a write request from the instruction execution unit II occurs within N machine cycles from the previous write request, the previous write request is still in the store buffer 12, and the write If the area is within the same 8 bytes, a degeneracy operation is performed.

The value of N is determined with reference to the calculation execution time of the device to which the present invention is applied. For example, the number of machine cycles to be executed in the innermost loop of Do loop processing in a general FORTRAN array operation is given. The value of M is determined in relation to the total number of words in the store buffer, and is kept within a range that does not impair the function of the store buffer, which absorbs the difference in processing speed between the central processing unit and the main memory. It will be done.

In the present invention, when there are more write requests than M words in the store buffer, the same operation as the conventional device is performed, so the effect of the store buffer is maintained even when the frequency of write requests from the instruction execution unit 11 is high. It almost never drops. In addition, after any write request is held in the store buffer for a certain number of machine cycles N or more, it performs the same operation as the conventional device. etc. will not remain in the store buffer forever.

In the above embodiment, the write request from the store buffer 12 is made to the main memory 13, but instead of the main memory 13, a buffer memory having a copy of a portion of the data may be used. Even if there is, if the buffer memory is such that access contention is a problem, the present invention can be applied effectively.

[Effects of the Present Invention] As explained above, the present invention improves the degeneracy effect of writing by retaining written information for a certain period of time or more in the store server, and improves the delay due to contention in the storage device. I can do it.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of a conventional store store memory along with devices directly necessary for its control, and Fig. 2 is a block diagram showing an embodiment of the present invention.Explanation of symbols: 11 indicates instruction execution 12 is a store buffer, 13 is a main memory, 15 is an associative memory circuit, 16 is a write data/muffer circuit, 17 is an input byte specification buffer, 24 is a valid bit, 25 is a registration pointer, 26 is a registration Word selection circuit, 27 is a registration counter, 28 is a read word selection circuit, 29 is a byte specification creation circuit, 33 is a read pointer, 34 is a read counter, 41 is a word number detection circuit, 42 is a store inhibit counter, 43 respectively represent the store buffer control circuits.

Claims (1)

[Claims] 1 A function for degenerately retaining write data associated with write access from a processing device to a storage device, and controllably issuing a write request to write the retained data to the storage device. A store muffer having a storage buffer is provided with a word count detection means for detecting the number of write accesses in the store buffer and a clock means for counting the time during which write accesses are held in the store buffer. and the means for controlling the write request is configured such that the number of write accesses detected by the word detection means is within a predetermined number and the time counted by the timer is equal to a predetermined value. A store buffer having a function of suppressing the write request when the write request has not been reached.