JPS585847A - Instruction branch mechanism - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION 10. Field of the Invention The present invention relates generally to data processing systems and, more particularly, to the instruction mechanism of a programmable data processor.

■6 Background of the present invention A computer instruction is a specification of an operation to be performed,
It may include one or more addresses at which the operation is performed, an address indicating the location/location of the result, and the address of the next instruction in the sequence.

These designations or addresses may be implicitly qualified.

That is, when specifying the next instruction location, the machine assumes that the instructions are sequential. In this case, the next instruction is assumed to be contained at the address following the current instruction's location.

The address of the current instruction is stored in a register called the Sequential Address Register (SAR). During execution of an instruction, the SAR is advanced by one address unit.

In any system that protects against SAR, there must be provision for setting and changing initial values at various points in the program in order to execute subroutines. This mechanism is a general command mechanism called the Pra/Chi mechanism. There are two basic types of branch instructions.

That is, there are branch instructions that involve stacking and branch instructions that do not involve stacking. These two branch instructions set a new value in place of the next sequential address of the SAR and define the starting point of the new sequence of instructions' locations. Instructions with stacking cause the next sequential instruction address to be stored in LIFO stack memory before the original instruction sequence is modified and can be used to execute a subroutine. This returns the system to the original sequence at the stored address. By definition, a branch instruction shall mean a branch instruction with a stacking operation in unknown it.

After completion of the subroutine/operation following the branch instruction, the program must return to the point in the original sequence of instructions from which the branch started. This is a "return command"
executed by The instruction address to which the program should return must be remembered at the time the branch instruction is executed. In order to make several consecutive branch instructions 0T capable, a last-in-first-out (LIF'0) instruction address stack must be provided to store their return addresses.

The usual way to provide an instruction address stack for pipelined instruction architectures is to
The first stage of the process is to have a large dedicated register file. This is because the first stage is the stage that determines the execution order. However, with the advent of large integrated circuits, significant savings in cost per degree can be achieved by integrating the instruction processing and arithmetic circuits of a processor onto an academic integrated circuit chip. However, mass storage functions such as data storage and instruction storage must be performed in separate memory chips.

This is because the available space on a processor chip is limited. Although it is desirable to maintain an immediately accessible record of return addresses in the first stage of the instruction co-event line, such mass storage
It is not easy to mix functions on the same integrated circuit chip containing instructions and processing elements. However, encapsulating the return/address storage function in a data storage mechanism could not be accomplished in the prior art, even if the data storage was provided on the same integrated circuit chip. This is because the return address could not be accessed from the data memory slot until several cycles or phases had passed after the return instruction was read by the first stage.

LIFO stack for data storage in data processing systems @
Storing in ditches is not a new idea.

For example, US Pat. No. 4,011,462 describes a method for performing subroutine linkage by using a LIFO stack in a data storage mechanism. The US patent does not consider the problem of concurrent pipelined instruction execution, which is a problem to be solved for sequentially phased instruction pipelines. The above US patent allows instructions to access a stack in a data storage facility.

This necessarily reduces the throughput of instructions in the instruction pipeline.

OBJECTS OF THE INVENTION It is an object of the present invention to provide improved sequence ordering for instruction execution high-lines in data processors.

Another object of the present invention is to provide an improved pipeline instruction mechanism for a data processor fully contained on an integrated circuit chip with reduced power dissipation.

Another object of the present invention is to utilize unused instruction phases to perform instruction pipeline/machine processing branch/return operations for a data processor.

Another object of the present invention is to provide a processor which is capable of accessing return addresses in a companion instruction stack located in a data storage mechanism that is accessed in a machine cycle following an instruction fetch machine cycle. It is to provide.

Another object of the invention is to reduce the efficiency of the pipeline.
The objective is to have data storage functions and cold stack functions performed by the same data storage device that can be accessed by multiple M-phase instruction pipelines without any FF.

(10) Summary of the Present Invention The above objects are achieved by the present invention disclosed herein. In the instruction pipeline for the data processor disclosed herein, instruction execution is performed in a series of phases as follows.

That is, these phases are the command [1! Fetch the instruction from if, calculate the data storage address from the fetched instruction, access the data storage@groove based on the calculated address, obtain the data operand, and access the data storage address according to the fetched instruction. Contains phases that perform logical operations on the data. Branch and return instructions are enabled by providing a return address stack during data storage. The data store stores the next instruction storage address to be returned after the branch operation is completed. Data record is @
The instruction address stack in the groove cannot be directly accessed by the instruction 7 etch stage of the pipeline until several instruction execution phases have passed without reducing pipeline efficiency. A stack register is provided at the instruction fetch stage of the line. This stack register contains a duplicate report of the instruction storage address currently placed on the top of the instruction address stack. When a return instruction appears in the branch quench stage, the address of the next instruction to be returned in the instruction register becomes immediately available without interrupting flow in the pipeline. The stack pointer placed in the intermediate stage (between the instruction fetch stage and the data storage access stage) is used to utilize the unused instruction M phase in the pipeline to Causes the next available instruction storage address to be read from the instruction address stack and loads it into the stack register in preparation for the next return instruction. Thus, data storage and instruction scooking functions are performed by the same data storage device accessed by intermediate stages in a multi-phase instruction pipeline without reducing pipeline efficiency. As an additional advantage, the partition size of the address stack in the data storage facility is reduced and the space saved can be used for data storage.

2. Description of the Implementation Column In this specification, an instruction pipeline for a data processor is disclosed. In this instruction pipeline, instruction execution is performed in a series of phases. These phases roughly fetch the instruction from the instruction m1llf, calculate the data storage address from the fetched instruction, access the calculated address in the data storage to obtain the data operand, and fetch the data operand. and performing logical or arithmetic operations on the accessed data in accordance with the instructions given. Blank and return instructions are made available for execution by providing a return address stack in the data location facility. The return address stack stores the address of the next command to be restored after the branch operation is completed. The instruction address stack in data storage cannot be accessed directly by the instruction fetch stage of the pipeline until several instruction execution phases have elapsed without reducing pipeline efficiency. A stack register is provided at the instruction fetch stage.

This stack register contains address duplication information for the instruction currently placed at the top of the instruction address stack. When a return instruction appears in the 8th instruction fetch stage, the address of the next instruction to be returned in the instruction store l11 beak is immediately available without interrupting flow in the pipeline. Stack placed in pipeline stage between instruction 7 etch stage and data storage access stage.

Pointers take advantage of unused instruction phases in the pipeline to populate the next available instruction address from the instruction address stack during the data storage access stage, preparing it for the next return instruction. Stack as
Load it into the register. In this way, data access functions and instruction stacking machine #7 can be performed by the same data access device accessed by intermediate stages in a multi-phase instruction pipeline, without reducing pipeline efficiency. Ru.

The Real-Time Signal Processor (R8P) is a general-purpose processor with a 16-bit data flow and a 24-bit instruction set. The conoflossor is code-wise matched to perform a slang processing algorithm. R8P is a pipeline/instruction unit designed to achieve high throughput without the need for high efficiency and high power circuits. Its architecture includes arithmetic, logic, control, and 32-bit division.
Complete lever of command) IJ-ffiimu. The processors of all the friends except for the memory lj are as shown in FIG.
It is provided on a single VLSI chip 5.

The R8P instruction set is an instruction that executes an arithmetic function in one cycle (multiplication 1, division, left shift) divided by 1<). In that case, one of the overwrite/dots is contained in the data store 8, and the other overload/domain is enriched in the stack register (local register) 18 shown in FIG. The result is returned to a local register. To execute such an instruction, the four distinct functions that must be executed are:

(1) 7-etch instruction (2) Formation of effective address for data use operation (3)
) Performing data storage accesses (4) Performing arithmetic operations and loading results For any one such instruction, the four functions listed above must be performed sequentially. The concept of pipelined instructions takes advantage of this property of instructions. The R8P architecture allocates a separate area of hardware to each @#Q. 4
While a stage executing one of the two instructions is operating on one instruction, other stages may be used to operate on other instructions at the same time. The execution of a given action is called the phase of that instruction. Phase 1 of the instruction is 7 etches of the instruction. Phase 2 is the generation of the effective address. Phase 3 is data memory access. Phase 4 is the execution of operation 1[E. The hardware stage performs four phases simultaneously for four different eyelid orders.

Since R8P is provided above the contested chip 5, space on the chip is at a premium. Therefore, data store (data usage @purchase) 8 warp instruction store (instruction list @W
The mass loading function of 6 is performed by the y31J (hard memory chip) which is accessed by the chip.

To maintain a record of return addresses for branch instructions, an address capacity of 64 is used.
The storage arrangement mechanism is required. This placement mechanism must be immediately accessible 0T by the first stage of the instruction pipeline. However, implementing such large scale functions on chip 5 uses a large amount of chip area and dissipates excessive power. On the other hand, in data store 8, litter 7 address LIFO is written! ! It would be considered inappropriate to perform such functions. Because, Litter 7
- The address cannot be accessed from the data store until the return instruction is read by the 'th' stage without reducing pipeline throughput.

This problem is solved by the present invention as follows. The address sequence control includes a 64 level stack 10 as shown in FIG. stack 1
0 is placed in data store 8 (memory locations 0-63). An exposed 16-bit hardware stack written to the top of stack 10 (directly located at the "Instruction Fetch and Sequence Control" stage)
It is held in register 18. The stack 10, addressed by a 6-bit stack pointer (SP) 28 (4th □□□), allows for 64 levels of subroutine and interrupt routes/total nesting.

Instructions that affect the stack are [unconditional branch and stack J (BS, l, ``return J (RET]), ``return and interrupt active'' (RET ENABLE). Unmasked interrupts also affect the stack. give.

The BS instruction reads the next sequential address (SAR1
6 (value of FIG. 3)] into the stack register 18 at the end of phase 2, and then executes an unconditional branch to the instruction address specified by the instruction's over/do a. Furthermore, by the end of phase 2, it causes the stack pointer 28 shown in FIG.
p = s p + 1), phase 3, 1 shift of 5AR16,
Stack 1 pointed to by stack pointer 28
Put 1 into address 0. In this way, stack pointer 28 always enriches the address of the top of stack 10.

The litter 7 (RET) type instruction uses the stack pointer 28
the address specified by (i.e. the top of the stack)
The entire contents of the file will be used as the address of the next order. Since this value is held in stack register 18 (FIG. 3), it will be used 0Tfffl in the next cycle. In phase 2, stack pointer 2.8 is decremented by 1 (SP=SP-1) to point to the next value on stack 10, and then in phase 3 of that instruction, that value is placed on stack 10. The stack register 18 is read from the stack register 18 at the end of phase 3 of a RET-type branch.

This causes a blank return address read from the stack 10 to become available for use by a subsequent RET-type instruction that occurs at least one instruction away from the previous RET-type instruction. This is because stack 10f: read,
This is because the first RET type instruction that loads its value into stack register 18 in phase 3 has time to update stack register 18.

In this way, chip 5 can immediately make stack 10 available OTe in its own fetch stage 1 without occupying extra chip area on the i,sI device. This utilizes the unused second and third stages of the R8P instruction pipeline during branch and return operations to access the stack 10, which is actually located in a partitioned area of the data store 8. This is achieved by

As shown in FIG. 1, a stored program data processor is formed on chip 5, which has a pipelined processor containing four time sequential stages. The first stage 1 is used for instruction sequencing and fetching, the second stage 2 is used for data store address generation, and the third stage 3 is used for data store access. Stage 4 of 4 is used for performing calculations. These stages operate in redundant mode on successive fc instructions, each containing operational code and operands. These instructions are accessed from an instruction store 6 external to the chip 5 to perform arithmetic operations on takes accessed from a data store 8 external to the chip 5.

The improved model is shown in detail in FIGS. 3, 4, and 5. A last-in-first-out instruction address stack 10 of FIG. 5 is provided in a partitioned area of data store 8 to provide address support for instruction store 6. Instruction address multiplexer 12 in FIG.
is placed in stage 1 and has its output 13 connected to the address input of instruction store 6. Multiplexer 12 has multiple inputs for inputting instruction addresses to instruction store 6. The instruction address incrementer 14 in FIG.
is provided at the output 13 of the multiplexer 12 and its input is
and its output is connected via sequential address register 16 to one of the inputs of multiplexer 12. This is because the instruction store address is sequentially increased by a unit amount.

Stack register 18 in FIG. 3 is provided in stage 1 and selects its input via a multiplexer (MUX) to the output of sequential address register 16 or to output 17 coming from stack 10 in data store 8. connected. It is for storing the last instruction store address output from incrementer 14 or the last instruction store address output from stack 10 of data store 8 via line 17. Furthermore, the stack
Register 18 has its output selectively connected to the input of multiplexer 12 or via line 19 to an enemy command address stack 10 in data store 8 . The stack register 18 records only the address of the row.

Self-instruction sequence/sing decoder (7-ke/shi7) in Figure 3
The controller 20 is in stage 1 and has its power connected to the command store 60 output cuff and its output 21 to the multiplexer 12. It is instruction store 6
address 13 through the multiplexer 12,
It is possible to selectively connect either the output of the sequential address register 16 or the output of the stack register 18. Its control is executed in response to the operational code of the instruction word after Fjt, which is accessed from instruction store 6 via line 7.

Multiplexer 12 can have one of its inputs connected to an output of instruction store 6 . It transfers the operands of the last instruction accessed from instruction store 6 to instruction store 6 in response to the associated operational code being decoded by instruction sequence/synog decoder 20.
It comes out for selective transfer as an address input.

Data store access decoder 22 in FIG.
is placed in stage 2 and has an input cuff connected to the output of instruction store 6. This is to decode the operation code that came from the last instruction accessed from instruction store 6. Data store address generator 2 in Figure 4
11 is placed in stage 2 and has an input connected to the output of the instruction store 6, a control input 25 connected to the data store accessing decoder 22, and an associated t operational code connected to the data store access decoder 22. - In response to being encoded by the accessing decoder 22, output 26 selectively generates the address of the data store 8 from the operand of the last accessed spinning word. Stack pointer 28 in FIG. 4 is placed in stage 2 and connected to data store access decoder 2.2, control power 25 selectively increases or decreases the data store address value to access the data. Output 2 for accessing the last instruction address stored in the stack 10 of store 8
It has 9.

Data store address register 30 of FIG. 5 is placed in stage 3 and has its input connected to output 26 of data store address generator 24 and its output connected to the address input of data store 8. Ru. It is intended to access the location of the data store 8.

In a branch operation, the instruction sequence decoder 20
selectively causes the operands of the unconditional branch operation to be forwarded to the address input 13 of the instruction store 12 via the multiplexer 12 by filling the associated branch operation code. l1il[l, sequential address
selectively controlling register 16 to be incremented by an amount, loading the contents of sequential address register 16 into stack register 18 in response to an associated branch operation code, and loading the contents of sequential address register 16 into stack register 18 in response to an associated branch operation code; to selectively control the non-destructive output of the contents of stack register 18 via line 19 to data input 32 of data store 8. In response to the branch operation code, data store access decoder 22 causes stack pointer 28 to be incremented by a drop amount and its contents to be stored in data store address register 30.
It selectively controls what is output as the location address of the host stack 10. This is to store the contents of stack register 1B as the litter 7 address from the branch specified by the branch address seed.

In the above branch operation, the stage 1 match search/sign/decoder 20 executes the control operation in the first phase when the branch operation occurs. The stage 2 data store accessor/decoder 22 performs its control operations in the second phase following the first phase. The data store address register (D
SAR) 3Ω is the location of the shared address stack 10.
accessing the shore, data store 8 stores therein the contents of stack register 18 at ff1 (i31HI) in the second phase. In this way, stages 2'& 3, which are otherwise unused, are During operation, the instruction stack 10 that is not located on the chip 5 is accessed.

In a return operation from a previous branch operation, stage 1 instruction sequencing decoder 20 loads stack register 1 during a first phase in response to a return instruction.
8 is selectively transferred to address input 13 of instruction store 6 via multiplexer 12.

Stage 2 data store access decoder 22 controls stack pointer 28 to be decremented by an amount in response to a return instruction operational code during a second phase following the first phase; And in order to access the last instruction address stored in the stack 10 of the data store 8, it fully controls the output of the contents of the stack pointer 28 to the data store address register 50 in stage 3.

Stage 1 instruction sequencing decoder 20 determines that in a third phase following the second phase, the last instruction address accessed from stack 10 of data store 8 is on line 17.
selectively controls loading into the stack register 18 via the . In this way, the stack 10
Even when the phase cannot be accessed in the data store 8, the return address can be used to access the curve store 6 if the return instruction occurs at least one cycle after the previous return instruction.

The following description describes in detail some of the elements/tools of a real-time processor.

Stage 1 shown in FIG. 3 executes only phase 1 of the execution of the order. At this stage, the 8-bit operation code of the previous instruction is decoded, the address of the current instruction is determined based on the condition code in the processor and the decoding result of the operation code of the previous instruction, and the current instruction is fetched from the instruction store 6. be done.

Program counter value (i.e. address of current instruction)
c. selected from the address in sequential address register 16 or one of a number of branch addresses; Address selection is performed under glodarum and/or interrupt control. In all cases, the address of the current instruction is determined entirely during phase 10 of instruction execution so that branching occurs in one instruction cycle.

During the second phase of instruction execution, valid data store addresses are computed for instructions requiring access to data store 8. The instruction's 16-bit operand field raJ is passed to address generation stage 2 shown in FIG.

The effective address for the data store operation is then formed based on one of four functions according to the ml directive. 'The four types of effective addresses are:

(1) a Direct memory (2) a + B Offset memory (3) a+
Xi i=1.2 Indexed memory (4
) M(a, Xi, B) i=1.2 Masked memory here, B is the pace register, M is the mask register.
register, Xi is the index register (i-1, 2
), M(aXX i, B ) are mask functions used for circular buffer operation.

In order to provide effective control over the various language processing data purchases, a number of registers are provided that update the registers used to form effective addresses (ie, X1, X2, W1, W2). These instructions complete execution in the second phase unless they involve a data store operation. The look at the data store is completed in the third phase. The operation of reading data store 8 is performed in phase 3 and stage 2.
The updated registers become available in the next cycle (phase). For data write operations, the effective address is generated by the stage 2 logic and sent to the data store address register 30 table at the end of phase 2 in preparation for the access in phase 3.

Data Store Stage (fi Phase 3) In phase 3 of instruction execution (memory access phase), data store 8 can be accessed with an effective address. Address generation stage 2
sends the effective address computed in the previous cycle (M phase) to data store stage 5 of Figure 5 for use in the current phase.For read-down operations, the data store output is The appropriate instruction is loaded into the appropriate class specified by the previous instruction's operation code. This is done at the completion of phase 3 of that instruction in preparation for use in phase 4.・Store 8
It does not access , but requires an immediate operand because it participates in the calculation of phase 4. In this case, data store stage 3 establishes a path from dormitory opera/doraji stage 2 to stage 4. It appears to use raJe in phase 4 of that instruction.

To maintain consistent execution of instructions, the execution of all four phases must be in a fixed relationship to each other.

Therefore, when an external device requests access to data store 8, it! The entire pipeline must be stopped. This process is called cycle stealing operation. data·
An I10 access to store 8 causes a cycle stealing operation, which delays pipeline execution by one machine cycle. All four phases/stages are delayed.

I of command execution! In the fourth (last) phase, arithmetic stage 4 is limited by instructions and performs the actual arithmetic operations. Most of the instructions in the arithmetic operation set are executed in the logic cycle of arithmetic stage 4. However, Multiply, divide, and shift left instructions each require multiple executions of this stage for it to complete.Multiply instructions require up to 8 cycles; divide instructions require 17 cycles; Left foot instructions require only one more cycle than shift count (D-31). For these instructions, the first three stage 2 logic 1.2.3 of instruction execution are "frozen". , while stage 4 of the current instruction is allowed to execute until the instruction completes.

The functions of I10 stage 34 can be divided into two types. They are direct I10 and external control I10.

The following explanations are a guide to each @Noh.

(1) Direct I10 This allows the processor to input a single word from an external device and output it to an external device under program control.

(2) External control I10 This allows the external device to directly control R8 under its control.
P(i--You can glance at the read out R8P.

Other R8P@Shake Other @purchases provided in R8P include real time clock, scan all registers.
Maintenance interface that can be latched to R8P while running out, and a set of FI&T
I101/Turf Eight allows an external device to control R8P by issuing an iQ command.

EXAMPLES OF PIPELINE OPERATION Two examples of the instruction pipeline operation are shown in FIG. Example 1
．． indicates the academic command being executed. Phase 1 through Phase 4 represent the four @functions performed on the Kinkima by the four hardware stages. Cycles are better/
・Means a cycle.

The instruction rAZ Z, a(Ml)j in this relay is the masked mail location M(a, Xl, B
) to the contents of the 1z register and place it in the accounting tz register. Accommodation operad raJ is register XI, B
, M and masked in stage 2, the effective address (e a ) = M(a.

Xl,B) is created and the storage location shore is accessed in stage 3. The sum is formed and loaded into the destination register in stage 4.

Example 2 shows a set of instructions that implement the following sequence of operations.

(1) ``LZ al (Ml) J This loads the masked memory location M(al, X 1, B) into two registers.

(2) rAz Z, N2 (Ml) J This writes the contents of the masked memory location M (N2, Xl, B) to 2 registers and places the result in 2 registers.

(3) rSTZ N3(Ml)J This stores the contents of the ZL/register into the masked memory location M(N3,XI,B).

(4) rB N4J This is the a-order address (
N4) Hebranochi.

A no-operation instruction rNOP,J is inserted into the instruction pipeline so that stage 4 of the pipeline can complete the rAZJ instruction before the N3 stage of the "STz" instruction performs the store operation that moves the result. Ru. Unused cycles retain their temporal position in the instruction pipeline.

The operation of the R8P hardware stage will now be explained in detail.

This explanation covers (1) how instructions are fetched and decoded, (2) how effective addresses are generated and used, and (3) how various condition codes and registers (such as the SAR1 stack) are set and interpreted.

This stage is illustrated in the flow diagram of FIG. It performs the functions of phase 1 of instruction pipeline execution. This stage includes instruction address selection logic that controls instruction store 6.

Instruction Store The instruction store 6, which is 24 bits wide, is divided by an 8-bit operation code field and a 16-bit over/under field. It is addressed by an instruction address multiplexer (program counter (PC) multiplexer) 12. The multiplexer output 13, which serves 16 pits, can address an instruction store 6 that addresses up to 65,536 instructions.

Instruction Address Selection Logic During phase 1 of instruction execution, the instruction address selection logic decodes the undetermined 8-bit operation code from the previous instruction to determine the source of the current instruction's address. The address is selected by multiplexer 12 and the instruction is accessed. branch, proceed
), or the operation code from the previous instruction that calls the litter7 operation, causes the address of the instruction being fetched to be looked at from one of the five branch sources. All other operational codes cause the address of the current instruction to be taken from sequential address register 16. Sequential address register 16 points to the address +1 of the last instruction latched.

Instruction address generation and fencing operations are performed in the same cycle to ensure that branching occurs in one cycle.

Multiplex 12 selects the address of the current instruction from among the following sources: All of these sources are 16-bit registers.

(1) Sequential address register 16 (
Next sequential address (pc+i)) (2)
Stack register 18 (top of 64-word instruction address stack) (3) Opera/do f'aJ register 36 (instruction obera/do field) (4) Save register 38 (contents of save register) (5)
IAR/Vector Register 4o (Vectorized Interrupt Address) 'Sequential address register 16 is selected as a source for sequentially addressing instruction store 6. Stack register 18 is selected as a source for return type instructions. The over/do "a" register 36 is selected as the source for the non-contingent bra/ch instruction. Additionally, it is used for all conditional branch instructions when the condition criteria are satisfied. If the condition criteria are not met, sequential address register 16 is selected.

The save register 68 is stored at 9 o'clock (i.e., r-
PJ-type instructions), is used as a source for the address of the next instruction. IAR/vector register 4o is used to mate the I/Q interrupt branch to words 1-63 of the share store. Instruction store refers to a branch instruction to the address of the appropriate interrupt handling routine.

Conditional Branching Conditional branching decisions are made based on the condition of the 8flil data/decatur pin.

These points are focused as a result of various conditions that exist in the processor when the instruction is executed. The condition indicator pinto is generated in stage 4 and includes nine condition code pintos and status flags generated in other stages. The branch conditions are as follows.

(1) Operation result = OZCC = 1 (2) Operation result < ONCC = 1 (3) Operation result match 0CC = 1 (4
) Internal overflow l0F=1(
5) Pending internal overflow POF'=1
(6) External overflow EOF=1(7
) i7 Denks comparison flag I CF=1(
8) Software Flags SF=1 All arithmetic instructions will send condition codes 1-5 at the end of phase 4. Multiplications, divisions, and left shifts that require multiple cycles of phase 4 to complete.

For any instruction, the condition code is sent after the fourth phase is completed. External overflow (condition code 6
] is determined in phase 3 and cented in phase 4. The index compare name (7) is generated in stage 2 and is sent in phase 2 of the instruction's execution. The software flag is sent below the phase 2 program side. Condition code 4.6.8 is launched and will remain in place until specifically protected. When specifically used, they are 0 helicented in phase 2 of the branch instruction that uses them. The focus of all other condition codes is sent by each operation/operation that affects it.

A conditional branch instruction is executed in phase 1 of the next instruction's execution, and is therefore executed based on the conditions that existed at that time. The various pla/chi orders are set in calculation stage 4 and executed based on nine condition codes. The branch is sent as the result of an arithmetic instruction that was decoded three or more cycles before the branch instruction. , the branch instruction CBI:CF) based on the index comparison flag is
Executed according to the conditions established as a result of the previous hanging.

A branch instruction based on an external overflow is executed based on a condition that was sent three or more cycles before the branch instruction.

Stack operation address seek/sequence conotronil
Clear the 64 level stack 10 placed in store 8 (
memory location 0-63).

The value written to the top of stack 10 was placed in stage 1. One 16-pin stack register 18
is maintained. The 64-level stack 10 addressed by the 6-bint stack pointer 28 has 64
Enables nesting of subroutines/and interrupt routines up to levels. Instructions that affect the stack 10 are "unconditional brachi and stack J (BS)", "return J"
(RET), [litter/&61J included tiQ motion J (R
In addition, unmasked interrupts also affect stack 10.

The B,S instruction causes the next sequential address (directly from sequential address register 16) to be placed on the stack: register 18 at the end of phase 2, and then the address specified by the address 'a' of the current instruction. Move an unconditional branch to the fc cold order address. Furthermore, it is phase 2
At the end of the box, increase the stack boi/re28 by 1 (SP=SP1i), and with fif3, sequential
The value of address register 16 is
Write to the address of stack 10 specified by 8. In this way, the updated stack boi/evening 28
always reads the top address of stack 1o.

A return-type instruction causes the contents of the address specified by the stack pointer 28 (ie, the top of the stack) to be used as the address of the next instruction. Since it is held in stack register 18, it is available for use on the next cycle.

In phase 2, stack boi/li 28 is stack 100
To specify the next location, it is decremented by 1 (S
P=SP-1), then during phase 3 of the instruction, the contents of the location / are read from the stack 10 and loaded into the stack register 18 at the end of phase 3 of the return type instruction. This allows the litter 7 address read from the stack 10 to be used by a later return-type instruction that occurs at least one hang instruction later than the previous return-type instruction. This is stack 10
This is because the first return-type instruction that reads and loads it into stack register 18 in phase 3 has time to complete updating the stack register.

But if a return-type instruction immediately follows another return-type instruction, the hardware must handle it in a special way. This means that when the second return-type instruction is decoded and quenched, the decoder 20 determines that the address of the association after the second return-type instruction is in the stack register 18 (directly). However, the stack register 18 still points to the second return instruction, so that instruction is fetched again. There is no problem with the first fetch of the second return type instruction. , the second fetch of the second return type instruction attempts to update the stack point/re2β in its phase 2 (phase 3 of the first fetch of the second return type instruction). , the stack pointer 28 will point to the wrong location.

Therefore, the decoder 20 decodes the second return type instruction.
In phase 2.3.4 of the fetch, a full no-operation/@ sign must be inserted on line Z instead of the normal return instruction. Thereby, decoder 22' inhibits stack pointer 28 from being updated a second time, and decoder 75 inhibits data store 8 from being read a second time.

As a result of this hardware-generated no-operation, the first fetch of the second return type instruction behaves normally, but the second fetch of the second return type instruction behaves normally in phase ``1''. It works like this, phase 2.3.
4 operates like a no-operation instruction. Third
Successive nine-star 7 type instructions are processed in the same way as the first return type instruction. This is because it is not a return type command, but follows a valid no-operation l1ff command. The operation of consecutive return instructions on two or more μ is as follows.

At the first ρ machine cycle, the value stored in the stack register 18 is St, then the stack.

The value stored in pointer 28 is i. stage 1
The decoder 20 in the previous life'? rt
7' and controls multiplexer 12 to line 13.
Enter the first address of instruction store 6 above. Thereby, the first instruction is fetched from instruction store 6.

At the beginning of the second cycle, the stack register 18 has recorded St, the stack pointer 28 has stored i, and the decoder 20 in stage 1:
The first command is given in the second cycle following the first cycle.

6 and t, and controls the multiplexer 12 to transfer the content Sik of the stack register 1B to the instruction store 6 as the second address. As a result, the second command is fetched from the anti-rust door 6. Arashi Stage 2
The decoder 22 in the second cycle controls the decoder stack pointer 28 with the first instruction as the first return instruction in the second cycle, and reduces its contents by a unit amount to "i-1". This value is output to data store address register 30 in stage 3 as the kth first data store address of stack 10.

At the beginning of the third machine cycle, stack register 1
8 stores Si, and the stack pointer 28 is (
i-1) is stored. Decoder 2 in stage 1
0 is the second instruction total 1. In the third cycle following the second cycle, the second transfer/instruction is decoded and the multiplexer 12 is controlled to transfer the signal occupying the stack register 18 to the address store 6 as the second address. . Therefore, the second instruction is again fetched from the instruction store 6. The decoder 20 placed in stage 1 is connected to line 7.
The NO-OP output is connected to a decoder 22 in stage two and an operation code decoder 75 in stage three. That is the third
When the second return command is detected in the cycle, the No.
This is a method for outputting the -OP signal to line 7. The Ruru decoder 22 in stage 2 converts the second instruction into the second instruction in the third cycle.
Decode it as a return instruction and get stack boi/ri28! IJ is used to reduce its contents by a unit amount to (i-2). This value is output to the data store address register 30 in stage 3 as the ninth data store address in the stack 10.

In the third cycle, the decoder 75 in stage 3 decodes the first combination as the first return instruction and controls the data store 8 to perform 1. Access the first data in stack 1o based on the first data store address (i-1), and output the first data as value S to the stack register 18 via @17 of stage 1. .

At the beginning of the fourth machine cycle, stack register 1
8 writes 81-1, removes it, and stack points 28 (
i-2) fjr:giHl. In the fourth cycle following the third cycle, the decoder 20 in stage 1 again generates the second instruction and the second return instruction for the second time.
multiplexer 12'.
T! (1m, the contents of stack register 18 S,
-1 is transferred to the instruction store 6 as the third address. This causes the third instruction to be fetched from instruction store 6. The stage 2 decoder 22 outputs I! No-OP signal on 7 and answer, 4th
The operation on stack pointer 28 is omitted in the cycle. The decoder 75 in stage 3 decodes the second instruction as a second frame 7 instruction in the fourth cycle,
Data store 8 is controlled to create a second data store.
The second data of the stack 10 is accessed based on the address (i-2), and the second data e, rtfsi-2 is stored in the stack register 1 via the register 19 of stage 1.
Output to 8.

On the fifth cycle, stack register 18 is 5
i-2 is written, and stack boi/ri28 is (i
-2). Decoder 20 in stage 1
In the fifth cycle following the fourth cycle, the third branch is decoded as the first next instruction, and the multiplexer 12
is controlled to input the first next instruction address to the instruction store 6. As a result, the fourth command is fetched from the command store 6. The Ruru decoder 22 in stage 2 is
In the fifth cycle, the third instruction is decoded as the first next instruction, and the data store address generator 24 of FIG.・Store address register 3o
have them appear.

Operation code decoder 75 in stage 3 omits operations on data store 8 in the fifth cycle in response to the No-OPN signal in @7.

In this example, the contents in stack register j 1181i and stack register 28 do not change in @6 machine cycles. In the 6th cycle following the 5th cycle, the lutecoder 20 in stage 1 decodes the fourth + as the second next combination and switches the multiplexer 12 to I[I?
1llll, then the second next order store address 6
to use human power. Thereby, the fifth instruction is fetched from m% store 6 to 7. Ruru decoder 22 in stage 2
In the sixth cycle, decodes the fourth instruction as the next combination of the second and controls the data store address 'tQ generator 2a to write the next data store address of @2. , to the data store address register 50 in stage 3. Operation code for stage 3
In the sixth cycle, the decoder 75 decodes the third instruction or the first next instruction and controls the data store 8 to input the third data based on the first next data store address. Allow access. In this way, a wire store accessinog operation for two consecutive return instructions is extended in time.

It should be understood that the aforementioned No-UP signal may be generated by the data store access decoder 22 instead of the a-order sequencing decoder 20.

The response described above for two consecutive litter commands can be automatically adapted to any number of consecutive litters. If there are 2Nf-specific consecutive return instructions, they will be executed in 3m machine cycles, and every third cycle will automatically generate a No-OPfi signal by the hardware as described above. . If there are 2N+1") consecutive return instructions, they will be executed in (3N+1) better than 7 cycles, where N is the number of No-OP times signals executed by the hardware. Ruri, (2N+1) is
This is the number of return instructions. It is assumed that N is zero or any positive integer.

When an unmasked interrupt is honored, the stack 10 is affected. It indicates that the appropriate return address of the interrupted program is incremented by 1, and the accessed stack address is incremented by 1.
Using a pointer (sp=SP+1), it is placed into the stack register 18 before being passed to the data store 8 as an address. Interrupts cause a branch to the appropriate interrupt entry address in instruction store 6.

2. Address Generation Stage (Stage 2) Stage 2 in FIG. 41 executes the second phase of execution of instructions. The main function of stage 2 is to calculate execution addresses for data store 8 operations. The operation of data store 8 occurs during the third phase of execution. Other functions performed in stage 2 are as follows.

(1) Index register operation (2) Index register test (3) Save register calculation (4) Index register/storage interface (5) Stack pointer update Figure 4 shows the functional stage 2 Show a flowchart. All control registers shown in this stage (except stack pointer 28) have a length of 16 pins. Stack pointer 28 is 6 pints long. The following table lists these control registers: It's a list of registers.

44 index registers (Xl, Demeru. The /70 calculator 52 has a logic function that determines "greater than", "less than", or "equal". Zero counter 52 is capable of forming a direct complement input to the right for subtraction. Separate control is performed for the carry to LSB.

This allows the zero-counter to implement "two's complement" arithmetic or to insert one pinto off-sen H-insertion.

One pint offset is used in the comparison function to create a "less than or equal to" function. 0 account calculator 5
2' is also a 16-bin "two's complement" adder.

The interface to the address generation logic is as follows.

(1) 16 bint obera/draJ in combination
Field (2) 16 pinto output to save register 38 (3)
Execution address output for stage 3 (16 bits) (4) 16-bit input and output bus for stage 3 (5) Operation code for control (6) Index comparison flag (rich in status register) (7) Software flags (referred to as status registers) To generate a valid data store address on line 26, one of four methods of addressing must be used. As explained above, all effective addresses are available at the end of Phase 2 of the start-up process.

Effective attress is used in phase 3, so stage 3
I will send it to you.

Index Register Operation The remainder of the functionality shown in FIG. 4 is used to perform other address generation arithmetic functions.

Index register arithmetic This function performs the 0-counter 52, index register [
Xl, X2] 44, increase '10' sister (Wl, W2
) 49 and by feedbanking the relot calculator 52 to the index register. The @Noh that can be practiced are as follows. X1=
Xi+a, X1=Xi+Wj, X1=Xi-Wj, i=
1.2 and j=1.2° These operations are implemented in phase 2 of the visitation run.

The result of the index register test adder 52 sets the index comparison flag (I
CF) is set and this flag is used by the conditional branch instruction rBIcFJ. The υΩ calculator 52 is
By subtracting the immediate value (or the contents of the appropriate increment register) from the appropriate index register, the selected index register and the operand ra Compare with increment register. A flag is sent for the result of the specified test.

This test occurs during phase 2 of the merge execution, and at the end of phase 2, the compare flag is sent. The BICFa instruction that branches based on the result of this comparison will be valid if the next instruction is coded ``Hi''.

The feedback path from the save register calculation zero counter 52 to the index register is also used for the save register 38.
It's TI2. The save register is loaded at the end of phase 2. This @Noh will be performed by ASV Kinutima.

The interface between the index register and the data store is done directly or via transfer register 5°. Interfacing with the transfer register allows all data to be temporarily stored there, if desired.
Also, set i to load data from there. When data store 8 is read, its contents are transferred to the appropriate index register at the end of phase 6.

Writing to the data store occurs in phase 3.

Transfer Register Transfer register 50 is used to provide a link between data store 8 and all control registers in stage 2. This path is bidirectional, and data can be transferred from the data store to any control register and from the control register to the data store via the transfer register.

Additionally, the transfer register is used as a temporary storage location for data provided between the data store 8 and all control registers. Data is loaded from the transfer register to the destination register in phase 2 of 11 orders. When transferring data from the ION register to the transfer register, an effective direct path is provided to the transfer register so that the transfer occurs in phase two.

A read of data store 8 is performed at the end of phase 3 by loading the data into the register specified by the current operation code.
Transfer the contents of the store. Data from transfer register
A look into the store occurs in phase 3.

In phase 4 of its execution, an instruction of the type raf
trequires. For these instructions, stage 2 must send operand raJ to the effective address view at the end of phase 2. This first shift is phase 3 and stage 3.
and to the appropriate register in stage 4 as specified by the instruction's operation code. It can be used in phase 4 if required.

Data store stage 3 of FIG. 5 includes a data store 8, a data store address register 30, and a manual selection multiplexer (MUX) 54. Stage 3 is data placement and quenching 111 for R8P.
produce a fruitful crop. Data store 8 is for 16 bit words +V and addresses oT up to 655361 words.
[is. A 16-pit data store address register 30, along with image selection logic, is provided to select between the effective address generated by stage 2 and the address provided by stage 10 logic 34. Image selection is performed by motion code decoder 75. Operation code decoder 75 controls multiplexer 54 and data store address register 50 in response to the operation code input on @7. For a glance operation into data store 8, the data source is selected from (1) stage 4, (2) stage 2, (3) stage 1 stack register 18, . . . (4) I10 logic stage 34. .

The output of data store 8 (lines 56 and 17) is routed to the appropriate register specified by the current operating code for use in the other four stages upon completion of phase 3. Write operations to the data store are stage 2
Occurs in phase 3 of the visit, using the effective address. The data being written becomes available in the source register at the end of phase 2.

The data fetch operation is performed in phase 3 of alloy execution;
The data is placed in the register specified by the current ff, Q, operation code. Data store 8 color stage 4
When loading data, the data is placed in the appropriate register at the end of phase 3, then passed through the adder (condition code is sent) in phase 4, and written to the destination register at the end of phase 4. .

Use of data store 8 by I10 logic stage 34 is accomplished by cycle stealing operations. When stage 34 requests a data store operation, the vibrator is stopped thg while data store 8 cycles are used by stage 34. After one cycle steal for an I10 operation, the pipe stream is restarted. Ninth, to maintain consistency and integrity in commands;
All stages of the pipeline must be stopped. .

6L command r A Z Z, "a (I) J (Immediately turn on +1 avz and put the result on z),"
Phase 4 operation (7) 7ta6 to stage 4 operand r
For those that require =Jk, a direct path is provided from the data store address register 60 to the appropriate register in stage 4. This path is placed on the dynamic address line by stage 2, making it available as input data to stage 4. This is because the operation does not use the data store 8 during its execution.

The A-order pipeline architecture of the real-time signal processor chip described so far provides access to a 64-level address stack located in partitioned areas of the data store, so that during branch and return operations , take advantage of command phases that are not underground. The address stack is actually placed a few instruction phases beyond the Kisha-Fench stage, but the contents of the address stack are stored with the help of stack registers placed in stage 1? available for immediate use. As you can see, on the Prosensor chip, the address
The stack consumes no extra chip area or power. Without the present invention, the address stack would be immediately utilized at the instruction fetch stage;
It must be provided on the processor chip. Furthermore, the partition size of the address stack in the data store can be reduced and the saved space can be used for other data devices.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram of the real-time signal processor, FIG. 2 is a diagram showing the instruction pipeline operation, and FIG. 3 is the l! ! II
FIG. 4 is a functional block diagram of the address generation stage, and FIG. 5 is a functional block diagram of the data store stage. 6...ftJe store, 8...data store, 10...Okinori address stack, 12...
Instruction address multiplexer, 14...Instruction address increase 7711B, 16...Sequential address register, 18...Stack register, 2
o...Kinrei Sequence/Sing Decoder, 22...
・Data store accessing decoder, 24-・
...Data store address generation 5% 2s...
Stack pointer, 60...Data store address register (υ5AR), 54...Input selection multiplexer, 75...Operation code decoder. Continued from page 10 Inventors Abraham Peired 10 27, Snose Rennie Court, California, USA 0 Inventors Frederick N. Lis 1466 Mohawk Road, Mohegan Lake, New York, USA 0 Inventors Michael Earl Cosgrove 2626 Alvey Drive, Highmarket, Virginia, United States

Claims (2)

[Claims] (1) Addresses of an instruction storage device for storing instructions, a data storage device for storing data, a k-th first stage for controlling the seven etchings and sequences of instructions, and the above-mentioned data write device? The second stage for generating the data register comprises a pipe-life instruction machine containing @3 stages for accessing the device, each of the stages containing a plurality of commands each containing an operation code and an opera/dot, respectively. a stored program data processor operating in a redundant mode for executing consecutive instructions, wherein instructions are accessed from said instruction storage device and instructions are executed on data accessed from said data storage device; an instruction address stack provided in a partitioned area of the data storage lid for storing instruction addresses of the instruction storage device; and a multiplexer provided in the first stage; a multiplexer having an output connected to an address input of the device and having a plurality of inputs for inputting instruction addresses to said instruction storage; and a sequential multiplexer for storing addresses of sequential storage locations in said instruction storage. - an address register and an address incrementer provided in said first station, said incrementing input connected to said multiplexer output and said incrementing said sequential address register for incrementing said instruction address; address multiplier with output connected to the power of the above multiplexer
The JO unit and the register provided in the first stage store the instruction address outputted from the address multiplier or the instruction address stack, so that the output of the sequential address register or the instruction address is stored. a stack register having an input selectively connected to an output from the address stack and having an output selectively connected to an input of the multiplexer or an input of the instruction address stack; a decoder disposed in the stage, the decoder having an input connected to an output of the instruction storage device and an output connected to the multiplexer, the decoder being responsive to an operational code of an instruction accessed from the instruction storage device; a first decoder for controlling an address input of the instruction storage device to be selectively connected to an output of the sequential address register or an output of the stack register via the multiplexer; The fc is accessed from the instruction storage device by a lever provided on the stage.
a second decoder having an input connected to an output of the instruction storage device for decoding operational codes of enemy commands and controlling access to the data storage device; a device having an input connected to an output of the instruction storage device and an input connected to the second decoder, the instruction storage device in response to decoding an operational code in the second decoder; an address generator for generating an address of the data storage device from an operand of an instruction accessed from the second stage; and a pointer device provided in the second stage, the pointer device having a control input connected to the second decoder; increasing or decreasing the address of a storage location in the data storage device;
a pointer device for specifying the storage location of the friend instruction address last stored in the instruction address stack;
a register provided in said third stage, having an input connected to an output of said address generator and an output of said voice retrieval device for accessing a storage location of said data storage device; an address register having an output connected to an address input of said data storage device; and a decoder provided in said third stage having an input connected to an output of said instruction storage device and an address register connected to said data storage device; IIJ 1 receives a connected control output and responds to an operation code of a branch instruction accessed from said instruction store so that the contents of said stack register are input to a data input of said data store.
111, and the multiplexer, in response to the decoding of the operation code in the first decoder, transfers the operands of the instruction accessed from the instruction storage device as a branch address to the instruction storage device. Forward. one of its inputs is connected to an output of the instruction storage device, the first decoder is responsive to the operation code of the branch instruction so that the operands of the branch instruction are transferred via the multiplexer to the output of the instruction storage device. the second decoder is responsive to the operation code of the branch instruction; , increasing or decreasing the void/return device so that the contents of the stack register are stored in the data storage device as a return address from the branch instruction specified by the operation code of the branch instruction. and controlling the output of the contents of said pointer device to said address register as an address of a storage location shore of said instruction address stack. ! L (2) An instruction storage device that stores instructions, a data storage device that stores data, and an instruction fetch/sequence device.
a first stage for controlling the address of the data storage device, a second stage for generating an address of the data storage device, and a third stage for accessing the data storage device; Each of the stages operates in a redundant mode to execute a plurality of consecutive instructions, each containing an operational code and an operand, and instructions are accessed from said instruction store and instructions are accessed from said data store and executed on said data. In the storage program type data processor in which the above is executed, an instruction address stack provided in a partitioned area of the data storage device and an instruction address stack for storing instruction addresses of the instruction storage device; a multiplexer provided, the multiplexer having an output connected to an address input of the instruction storage device and having a plurality of inputs for inputting instruction addresses to the instruction storage device; a sequential address register for storing addresses of sequential storage locations in the first stage;
an address increment connected to the output of the multiplexer to increment the instruction address, and an address increment connected to the input of the multiplexer via the sequential address register to increment the instruction address; and a register provided in the first stage for storing the instruction address outputted from the address incrementer or the instruction address stack. a stack register having an output selectively connected to an output from the instruction address stack and an output selectively connected to an input of the multiplexer or an input of the instruction address stack; a fixed decoder mounted on the stage and configured to develop an input connected to the output of the multiplexer so that the address input of the instruction store is connected to the multiplexer in response to an operating code of an instruction accessed from the instruction store; i to be selectively connected to the output of said sequential address register or to the output of said multiplexer via
+ a first decoder for controlling the data allocation device; and a decoder provided in the second stage for decoding an operational code of an instruction accessed from the instruction storage device to control access to the data allocation device; a second decoder having an input connected to an output of the instruction storage device;
an address generator disposed in the stage having an output connected to the output of the instruction storage device and an input connected to the second decoder, the address generator being responsive to the decoding of the operational code in the second decoder; an address generator for generating an address for the data arrangement device; and a point/reference device in the second stage, the point/reference device being connected to the second decoder and having nine control inputs, for generating an address for the data arrangement device. a register provided in the third stage; a register provided in the third stage; a register provided in the third stage; In order to access the recorded location of the data storage device, an output connected to the output of the address generator and an output of the pointer device is connected, and an output connected to the address input of the data location device. an address register having an address register, and a friend decoder provided in said third stage having a friend power connected to an output of said instruction storage device, and a control output connected to said data arrangement device, said instruction storage device; a third decoder for controlling input of the contents of said stack register to a data input of said data arranger in response to an operation code of a branch instruction accessed from said branch instruction; a branch address register for storing an address, the multiplexer for transferring the contents of the branch address register to the instruction storage in response to decoding of the operation code in the first decoder. , one of its inputs is connected to the branch address register, the first decoder is configured to determine, in response to an operation code of a branch instruction accessed from the instruction storage, the contents of the branch address register as described above. controlling the transfer to the address input of the instruction storage device via a multiplexer, and controlling the transfer of the sequential
The second decoder controls loading of the address in the address register into the stack register, and the second decoder controls loading of the address in the address register into the stack register in response to the operation code of the branch instruction. (2) controlling the increase or decrease of said pointer device, and controlling said pointer device to be stored as a return address from a branch operation specified by a code in said data arrangement device; An instruction branch characterized in that it controls the output of contents to said address register as an address of storage location, 7, of said instruction address stack! ! ! 111f.