CN100559377C - Integrated circuit and electronic device and method for designing integrated circuit - Google Patents
Integrated circuit and electronic device and method for designing integrated circuit Download PDFInfo
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Abstract
集成电路(300)具有规则的网格，该网格由基本一样的构造块(100a-i)形成。要避免可能发生在集成电路(300)边缘的路由冲突，该冲突是由使用单一类型的非对称构造块所引入的，该集成电路(300)与路由单元(200)扩展，提供在网格边缘的路由，这个边缘未被构造块(100a-i)的路由网络覆盖。路由单元(200)和开关单元(250)由第一路由结构(330)和第二路由结构(340)组合在一起，以形成环绕在集成电路(300)的网格周围的路由网络(280)。因此，集成电路(300)表现为只包括单一类型的构造块(100a-i)，但仍具有完全对称的路由结构。
An integrated circuit (300) has a regular grid formed by substantially identical building blocks (100a-i). To avoid routing conflicts that may occur at the edges of the integrated circuit (300) due to the use of a single type of asymmetric building blocks, the integrated circuit (300) is extended with routing cells (200) to provide routing at the edges of the grid that are not covered by the routing network of the building blocks (100a-i). The routing cells (200) and the switch cells (250) are combined by a first routing structure (330) and a second routing structure (340) to form a routing network (280) surrounding the grid of the integrated circuit (300). Thus, the integrated circuit (300) appears to include only a single type of building blocks (100a-i), but still has a completely symmetrical routing structure.
Description
Technical field
The present invention is relevant with a kind of integrated circuit, and this integrated circuit comprises a plurality of essentially identical interconnective tectonic blocks (building block), and they are distributed on the grid of rule, and each tectonic block comprises: logical block; Be coupled to first route device on this logical block, be used for the data communication between another the 1st logical block of first direction on this logical block and the grid; Be coupled to the secondary route device on this logical block, be used for the data communication between another second logical block of second direction on this logical block and the grid; And switchgear, first route device that is used to be coupled is to the secondary route device.
Background technology
At semiconductor applications, people have carried out a large amount of effort and have created multiple integrated circuit.Because integrated circuit (IC) and the cost that has an electronic equipment of sort circuit are all increasing, press for the integrated circuit that to finish a plurality of tasks, to utilize this hardware as far as possible once more.A kind of possible realization of this target is by using reconfigurable IC, as field programmable gate array (FPGA).Sort circuit generally includes a plurality of tectonic blocks, and this tectonic block comprises the programmable logic cells that can carry out a plurality of tasks, and programmable route hardware is to provide interconnecting or route network between the tectonic block.Usually these tectonic blocks are arranged in the mode of rule, and as grid, to guarantee interconnecting apart from shorter between these different tectonic blocks, this helps the performance of IC to improve.The very important point is that route network is complete as far as possible, should keep shorter as far as possible as the data routing between the tectonic block, because reduced between the tectonic block data transmission like this to the IC Effect on Performance.
The complicacy that designs this IC is that total although the symmetry of this grid is very high, the symmetry of tectonic block itself is very low usually.For example, tectonic block on a limit, have route device with on first direction to or from logical routing unit forwards data, on second limit of tectonic block, also have another route device, with on second direction to or from logical routing unit forwards data.Other limit that this means this tectonic block lacks route hardware, this will produce routing issue on the edge of grid, these edges are made up of the edge of the tectonic block that lacks route resource, especially, if the data that those tectonic blocks require and grid is outer communicate especially like this.Sometimes this means that some task can not be mapped on this IC, because the foundation structure of this special desired route of task is unavailable.Though this problem can be by solving with this tectonic block of route hardware expanding on its all limits, but this solution is considered to not meet needs, because it has increased the area of silicon greatly, this had both increased the complexity of IC, had also increased complicacy and the expense of IC.
Patent US 6002268 provides a solution of this problem, promptly discloses a FPGA with infilled frame (padframo) expansion around the grid of FPGA.The special duty of these infilled frames is to provide the path to connect between the tectonic block of grid and the I/O unit outside the grid.This is a shortcoming, only provides limited function because these infilled frames have increased the area of silicon.One of main bottleneck that should be pointed out that the logical design that design is reconfigurable is than task equipment, and its useful area is littler, and this has emphasized that the solution that needs to increase useful area solves above-mentioned routing issue.
Summary of the invention
In particular, target of the present invention is according to the introductory song paragraph, and a kind of integrated circuit that more are centered around grid many usefulness routing functions on every side that have are provided.
The present invention is described by independent claims.Attached requirements definition advantageous embodiments.
The present invention is based on following understanding: the integrated circuit with repetitive structure can design by the combined structure piece, to form desired IC.Main design focal point is the design of tectonic block, and this tectonic block should be carried out a plurality of desired finishing of tasks.This comprises the design of logical block, also comprises the design of first and second route devices.After this finishes,,, directly construct grid with the form of similar ceramic tile (tile-like) by the composite construction piece.Thereby, formed first route device of these tectonic blocks of combination on first limit of this grid and the secondary route device of these tectonic blocks of combination that formed second limit of this grid and be combined into part route network around this grid.This route network is finished as the route piece by using routing unit, and to be communicated to not the edge of the grid that is covered by the part route network, this part route network is combined by first and second route devices.This scheme has following advantage, promptly this route network can form by combination route hardware at an easy rate, and these route hardware are ready-made, have special route piece, they generate a kind of route network, can be used in the grid simultaneously and grid communicating by letter outward.Switch element improves route network, and switch element has the function that certain part of route network is coupled to another part.This switch element can be an independently piece, but also can be integrated in certain routing unit, and perhaps in the tectonic block of this grid, it is coupled to one of first and second subclass of a plurality of tectonic blocks with the subclass of a plurality of routing units usually.
What should emphasize is, although comprise the quantity that extra routing unit and switch element have increased the tectonic block that will design, this is not a shortcoming, because routing unit and switch element have relatively low complicacy.Therefore, they can be devised soon, and because their availability has reduced the desired design effort of exploitation tectonic block, total design effort might not increase.In addition, because this grid can use the tectonic block of single type, the extensibility of this IC is enhanced, and this is a very important advantage when relating to design reuse.
If each in these a plurality of routing units is arranged as an adjacent logical block that connects at least on the grid and arrives the outer hardware of grid, this is favourable.Routing function though routing unit can be used to upgrade on the grid, and routing unit is more suitable for being used for improving the route between the outer hardware of tectonic block on the grid and grid.This has increased the dirigibility of IC, allows the bigger task of mapping scope on IC.Should be pointed out that a routing unit can be utilized for a plurality of tectonic blocks route is provided, promptly several tectonic blocks can be shared a routing unit.
The place that another one is favourable is, if integrated circuit further comprises a plurality of interconnecting members, they are arranged the hardware of tectonic block outside grid that is used for connecting from first subclass and second subclass.
Though connecting and composing the interconnected hardware of the hardware of tectonic block outside grid of first and second subclass can be contained in these tectonic blocks, but people more are ready to provide these interconnected hardware by the mode of interconnecting unit independently, as the brick (tile) of this interconnected hardware is provided.This has the following advantages, and the tectonic block that promptly constitutes grid can keep similar as much as possible.Obviously, such interconnect function preferably appears on the edge of the grid that routing unit covers.Extra interconnecting unit can be used on those edges, although people more are ready the integrated route of interconnect function by the unit.
If the switchgear here comprises a plurality of programmable switches, be again another advantage.
Comprise that in switchgear but programmable switch makes this switchgear repeated configuration, therefore, get by the routing variable on the grid between the different tectonic blocks of first route device and secondary route device very flexible, thereby further increased the dirigibility of IC by allowing the wider task of mapping on IC.
In the another embodiment of the present invention, it is the shape of rectangle basically that tectonic block has; These a plurality of routing units comprise: first subclass of routing unit is used for three subsetss via the integrated tectonic block in first limit of rectangular shape to route network; Second subclass of routing unit is used for the 4th subclass via the integrated tectonic block in second limit of rectangular shape to route network; Article one, the limit is different from the second limit on length.
If tectonic block is not square but rectangle, be necessary then to use that to avoid mapping (mapping) more than the size of one routing unit be layout (layout).Obviously, the width of routing unit is normally by towards the width definition of the tectonic block at grid edge.For the tectonic block of rectangle, this has caused two subclass of routing unit, and their width mates the size on the limit of tectonic block respectively.
Electronic equipment, as system on a chip, desired performance is more and more higher, be not only aspect speed, and aspect the versatility of function.A plurality of task in such equipment, comprises the function versatility that to improve this design according to integrated circuit of the present invention, because can be mapped on the IC.Therefore, this electronic equipment only needs less specialized hardware, and this has reduced the actual amount of the silicon of this electronic equipment, thereby, producing such equipment, can lack than the design cost that lacks according to IC of the present invention.
Method for designing of the present invention allows directly design to have the IC of very high symmetry grid, this has reduced the workload of design IC, particularly be added in the grid, especially be fit to use graphic user interface with certain functional description when routing unit and switch element can be used as brick (tile).Therefore, the Time To Market of the IC by this kind method exploitation has reduced, and this is a very important advantage.
A first aspect of the present invention provides a kind of integrated circuit, comprising: a plurality of identical interconnective tectonic blocks are distributed on the grid of rule, and each tectonic block comprises: logical block; Be coupled to first route device on this logical block, be used for the data communication between another the 1st logical block of first direction on this logical block and the grid; Be coupled to the secondary route device on this logical block, be used for the data communication between another second logical block of second direction on this logical block and the grid; And switchgear, first route device that is used to be coupled is to the secondary route device; This integrated circuit is characterised in that first subclass of a plurality of tectonic blocks has its first route device respectively, and makeup ring is around the part of the route network of grid; Second subclass of a plurality of tectonic blocks has its secondary route device respectively, and makeup ring is around another part of the route network of grid; This integrated circuit also comprises a plurality of routing units, and this part and this another part that it is coupled to route network are used to finish the route network around grid.
A second aspect of the present invention provides a kind of electronic equipment, comprising: data communication equipment (DCE); Be coupled to the data storage elements of data communication equipment (DCE), be used to store data; Be coupled to the treatment element of data communication equipment (DCE), be used for coming deal with data by carrying out special duty; As the integrated circuit that first aspect provides, be used for further coming deal with data from the task of a plurality of tasks by carrying out, can select task by disposing this integrated circuit, this integrated circuit is coupled to data communication equipment (DCE).
A third aspect of the present invention provides a kind of method of designing integrated circuit, comprising: design a plurality of identical interconnective tectonic blocks, each tectonic block comprises: logical block; Be coupled to first route device of this logical block, be used between another first logical block of first direction on this logical block and the grid, carrying out data communication; Be coupled to the secondary route device of this logical block,
Be used between another second logical block of second direction on this logical block and the grid, carrying out data communication; Switchgear is used to be coupled first route device to the secondary route device; On regular grid, arrange a plurality of tectonic blocks; The method is characterized in that, further comprise the steps: by comprising the route network of following content design around grid: first subclass of a plurality of tectonic blocks, have their first route devices separately, form the part of route network; Second subclass of a plurality of tectonic blocks has their secondary route devices separately, forms another part of route network; Be coupled to this part of route network and this another part with a plurality of routing units, be used to finish route network around grid.
Description of drawings
The present invention is with reference to accompanying drawing, and the mode of the example by indefiniteness is elaborated, wherein:
Fig. 1 explanation has the example constructions piece of the IC of this tectonic block;
Fig. 2 a-2c explanation is according to dissimilar routing unit of the present invention;
Fig. 3 shows the IC according to route network around of the present invention;
Fig. 4 shows another IC according to route network around of the present invention;
Fig. 5 explanation has the electronic equipment according to IC of the present invention.
Embodiment
But Fig. 1 shows a kind of tectonic block 100 of grid of repeated configuration circuit, the equipment that like FPGA is the same with fine and closely woven granularity, but perhaps a kind of repeated configuration circuit of more coarse granularity, usually tectonic block 100 comprises logical block 120, this logical block can be carried out a plurality of tasks, can come selection task from these tasks by disposing this logical block 120.The logical block 120 of tectonic block 100 is coupled to first route network 130 by a connecting box (connoction box) 150V, with activate with grid in other tectonic block at first direction, as vertical direction, data communication.In addition, logical block 120 is coupled to secondary route network 140 by a connecting box 150H, with activate with grid in other tectonic block in second direction, as horizontal direction, data communication.First route network 130 and secondary route network 140 are coupled by a plurality of programmable switches 162 that are positioned at switch enclosure 160.Use the feasible route that can dispose grid of programmable switch, i.e. data communication between the tectonic block connects.Tectonic block 100 further comprises a plurality of interconnection 122, is used on grid this tectonic block being coupled to other tectonic block.
What should emphasize is that the architecture of tectonic block 100 is just as nonrestrictive example.Other the well-known architecture that is used for the tectonic block of regular grid is acceptable equally, and this can not depart from instruction of the present invention.In addition,, will be appreciated that the routing infrastructure of being made up of route network 130,140 and switch enclosure 160 is highly schematically to describe for those those skilled in the art, and as nonrestrictive example; Can find out more complicated structure, wherein can present unidirectional, two-way and routing infrastructure buffering, and not exceed scope of the present invention.
The grid of reconfigurable circuit is more suitable for being made of essentially identical tectonic block, as tectonic block 100, because a spot of design effort of these needs.But as seen in Figure 1, this tectonic block is normally asymmetrical, because two limits of route network 130 and 140 covering structure pieces 100.This asymmetry will be reflected in the grid, and it also is asymmetrical substantially, thereby cause lacking route hardware at the edge of the grid of being made up of the limit of tectonic block, and these tectonic blocks are not routed the network coverage.Therefore, up to now, the grid of reconfigurable circuit is to use polytype tectonic block to construct, to guarantee to realize the complete route network on the grid, or use proprietary route network around grid, with the routing issue of avoiding causing on the grid edge because of the tectonic block 100 that uses single type.
Yet, use as the described unit of the present invention of Fig. 2 a-2c, the feasible tectonic block 100 that can use single type, and do not need to use proprietary network around grid, because use these logical blocks to solve the routing issue on the limit that is not capped on the grid.A kind of routing unit has been described in Fig. 2 a.This routing unit 200 comprises route lines 210, and it is coupled to switch element 230, and it comprises programmable switch 232.Such switch element 230 also can be used as independently tectonic block, to be connected to each other adjacent routing unit, does the shortcoming of the number that increases dissimilar tectonic blocks although it is so.In addition, routing unit 200 comprises connecting box 220, arrives routing unit 200 with a logical block that connects tectonic block 100.Routing unit 200 preferably has interconnection 240, with route network the hardware to grid outside of abutment ring around grid, though this function also can realize (following displaying) by using interconnecting unit.Should emphasize that consistent with the routing architecture of logical block 100 as the layout of the routing unit 200 described at Fig. 2 a, this is just as example.Obviously, if the routing architecture of logical block 100 changes the also corresponding change of the structure of routing unit 200 (as showing below).
In Fig. 2 b, shown the switch element 250 that comprises programmable switch 252.Such switch element can be as the different sections of interconnected ring around the route network of grid.In the solution of first-selection, only switch element 250 of needs is finished the route network around grid.Should emphasize that switch element 250 can be integrated in the routing unit 200, this can not exceed scope of the present invention.
In Fig. 2 c, shown interconnecting unit 260.Such interconnecting unit can be used for interconnecting tectonic block 100 on the grid edge to the outer hardware of grid.Interconnecting unit 260 can be integrated in the tectonic block 100 on the grid edge.This will make that these tectonic blocks 100 are basic identical with other tectonic block in the grid.Yet, preferably allow interconnecting unit 260 as autonomous unit, so that only design the tectonic block 100 of single type.In addition, if these unit itself lack such function, interconnecting unit can be at the grid edge that is covered by routing unit 200 as autonomous unit.
The example combination of in Fig. 3, having showed the grid that different units described in Fig. 2 and the tectonic block described in Fig. 1 form.Integrated circuit 300 has a plurality of tectonic block 100a-i, and they are organized on the grid of a rule.Tectonic block 100a, d, g, 100b, e, h and 100c, f, first route network of i have formed the routing infrastructure of vertical direction by tectonic block 100a-i switch element separately.Tectonic block 100a, b, c, 100d, e, f and 100g, h, the secondary route network of i have formed the routing infrastructure of horizontal direction by tectonic block 100a-i switch element separately.The non-symmetrical features of each tectonic block 100a-i is reflected on the asymmetry of grid of formed IC 300.This grid edge and left hand edge thereon lacks routing infrastructure.
Now, according to the present invention, the routing infrastructure that has been presented on the grid edge is used to the route network 280 of makeup ring around whole grid.The first of route network 280 is made up of routing infrastructure 330, and it comprises a plurality of tectonic blocks, i.e. tectonic block 100c, f, i, first route network of first subclass.The second portion of route network 280 is made up of routing infrastructure 340, and it comprises a plurality of tectonic blocks, i.e. tectonic block 100g-i, the secondary route network of second subclass.In addition, by routing unit 200 being coupled to coboundary and the tectonic block 100a of tectonic block 100a-c, d, the left hand edge of f, routing unit 200 are used to provide route device at the coboundary of grid and left hand edge.Like this, routing unit 200 also becomes the part around the route network 280 of grid.Another routing infrastructure 340 is coupled to the part of route network 280, and this network is formed by switch element 250 by routing unit 200, has finished route network 280 like this.For the sake of simplicity, route network 280 is described by a single solid line.The structure of IC 300 is finished by interconnecting unit 260, these interconnecting units be coupled respectively tectonic block 100g-i and 100c, and f, the i hardware outside grid is as data communication bus or other communication hardware.Therefore, reconfigurable IC 300 has very high symmetry and very big route dirigibility, this means that a plurality of application can be mapped on the grid of IC 300.
Among the shown embodiment, routing unit 200 comprises an interconnecting unit as interconnecting unit 260, so that the required interconnection between grid and the external hardware to be provided in Fig. 3.Yet, should be pointed out that this is not essential strictly speaking; Routing unit 200 needn't comprise such function, and in this case, interconnecting unit 260 can find at all edges of grid.And should emphasize that the layout of other of routing unit 200 also is possible, this kind layout can not exceed scope of the present invention; Routing unit 200 as the grid left side can be along single tectonic block alignment, and in this case, switch element 250 will be positioned at the upper left limit of IC 300.Obviously, the title as the left side, the right, top, bottom should not be considered to a kind of restriction, and they are to be used in order to illustrate simple purely.In addition, routing unit can be designed as not only tectonic block 100 of covering, for example by comprise a plurality of switch elements 230 in routing unit 200.In this design, routing unit 200 will typically be a plurality of tectonic blocks route will be provided, and the number of tectonic block equals the number of the switch element 230 that comprised.
If forming the tectonic block 100 of the grid of IC 300 is rectangle rather than square, then be necessary to use the routing unit 200 of two kinds of sizes.The schematic example of this IC 300 provides in Fig. 4.
First subclass of routing unit 200, be that the routing unit 200a-c three subsetss that to be used as by the integrated a plurality of tectonic blocks in first limit of its rectangle be tectonic block 100a-c are to route network, second subclass of routing unit 200, be that to be used as by the integrated a plurality of tectonic blocks in second limit of its rectangle be tectonic block 100a to routing unit 200d-f, d, the 4th subclass of g is to route network, and first limit is different from second limit on length.Usually first subclass of routing unit has length w1, and corresponding to the width of tectonic block 100, second subclass of routing unit 200 has length w2, corresponding to the length of tectonic block 100.
Same situation is applicable to interconnecting unit 260.First subclass of interconnecting unit 260, be that first limit that routing unit 260a-c is used as by its rectangle connects a plurality of tectonic blocks, the subclass that is tectonic block 100a-c is to the outer hardware of grid, second subclass of interconnecting unit 260, be that second limit that interconnecting unit 260d-f is used as by its rectangle connects a plurality of tectonic blocks, be tectonic block 100c, f, another subclass of i is to the outer hardware of grid.
Fig. 5 has shown a kind of electronic equipment 500, and it has according to integrated circuit 300 of the present invention.Integrated circuit 300 is coupled to data communication bus 560, or another kind of data communication architecture structure, is processing units 520 as them, be used to usually carry out proprietary task, and data storage cell 540, as RAM, ROM or other memory device.Electronic equipment 500 can be a mobile phone, a navigational system or another equipment of handling numerical data, they all can benefit from integrated circuit 300 according to the present invention, because integrated circuit 300 combines the dirigibility of route significantly, this has increased the number of the task that this kind reconfigurable circuit can finish, reduce price simultaneously, because the design effort of sort circuit is less relatively, this is based on the following fact, promptly has only one type the tectonic block that is used for grid to be designed.Therefore, electronic equipment 500 can competitive price come into the market, and multiple function is provided, because a plurality of task can be mapped on the IC 300.
Religious doctrine of the present invention allows the very effective method for designing as integrated circuit He other reconfigurable circuit of FPGA.
Such as already mentioned, in the design of sort circuit, main bottleneck is the design of forming the tectonic block of integrated circuit grid.The routing issue that the logical block by the design single type of avoiding following above-mentioned asymmetry and coming is introduced will design the tectonic block type of replenishing mutually of two kinds of symmetries at least.So just increased the complicacy of design process, and the Time To Market of relevant integrated circuit, this is a shortcoming, because short Time To Market is the key factor of semiconductor product success on the market.
In the method for the invention, the first step comprises a plurality of the same basically interconnected tectonic blocks of design, each tectonic block comprises logical block, this tectonic block is coupled to first route device on this logical block in addition, is used for the data communication between another the 1st logical block of first direction on this logical block and the grid; Be coupled to the secondary route device on this logical block, be used between another second logical block of second direction on this logical block and the grid data communication, this tectonic block also comprises switchgear, first route device that is used to be coupled is to the secondary route device.In other words, a kind of tectonic block of single type is devised, and has reduced the desired design effort of exploitation integrated circuit.Thereby a plurality of tectonic blocks are distributed on the grid of rule.
In addition, avoid the asymmetrical negative consequences of route on the grid layout, this method comprises by comprising the step of following content design around the route network of grid: first subclass of a plurality of tectonic blocks, and they have first route device respectively, form the part of route network; Second subclass of a plurality of tectonic blocks, they have the secondary route device respectively, form around another part of the route network of grid; With a plurality of routing units and switch element, be used to finish route network around grid.Be presented on the route hardware on the grid edge, eliminated the asymmetry of the route of the grid of building by the single type tectonic block with the combination of proprietary routing unit and switch element.Proprietary routing unit is relative simple module with switch element, can be easy to be devised in independent design procedure.Thereby method of the present invention relates to the tectonic block design of the single type of a routing architecture complete, symmetry that only combines this integrated circuit.
Should emphasize that the module feature of the different elements that makes up in the integrated circuit with method design of the present invention makes this method be particularly suitable for being integrated into computer-aided design (CAD) (CAD) instrument, with the integrated circuit of designing institute expectation.
Should be noted that embodiment above-mentioned is illustrative, rather than restriction the present invention, those those skilled in the art will design many alternative embodiment and not depart from the scope of claims.In the claims, the quotation mark that is arranged in bracket should not be interpreted as limiting this claim.Word " comprises " does not get rid of unit listed in the requirement or the content outside the step.The a plurality of such elements of use do not got rid of in the word of certain element front " ".In enumerating the equipment claim of several means, some in these devices can be embodied by the identical items of and hardware.The simple fact that certain methods is quoted from alternately in different independent claims does not indicate that the combination of these methods can not be used to benefit.
Claims (9)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP02077571 | 2002-06-28 | ||
| EP02077571.4 | 2002-06-28 |
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| CN100559377C true CN100559377C (en) | 2009-11-11 |
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| US (1) | US7355443B2 (en) |
| EP (1) | EP1520298B1 (en) |
| JP (1) | JP4283220B2 (en) |
| CN (1) | CN100559377C (en) |
| AT (1) | ATE483251T1 (en) |
| AU (1) | AU2003237005A1 (en) |
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| WO2009001368A2 (en) * | 2007-06-28 | 2008-12-31 | Indian Institute Of Science | A method and system-on-chip fabric |
| US7970979B1 (en) * | 2007-09-19 | 2011-06-28 | Agate Logic, Inc. | System and method of configurable bus-based dedicated connection circuits |
| US8131909B1 (en) | 2007-09-19 | 2012-03-06 | Agate Logic, Inc. | System and method of signal processing engines with programmable logic fabric |
| US8024690B2 (en) * | 2008-05-19 | 2011-09-20 | Arm Limited | Method, system and computer program product for determining routing of data paths in interconnect circuitry providing a narrow interface for connection to a first device and a wide interface for connection to a distributed plurality of further devices |
| TWI406146B (en) * | 2009-02-20 | 2013-08-21 | Accton Technology Corp | Method for design a modulation circuit |
| FR2954023B1 (en) * | 2009-12-14 | 2012-02-10 | Lyon Ecole Centrale | INTERCONNECTED MATRIX OF RECONFIGURABLE LOGIC CELLS WITH CROSS INTERCONNECTION TOPOLOGY |
| BR112014024312B1 (en) * | 2012-03-30 | 2022-04-12 | Intel Corporation | System and method of implementing a programmable device matrix in an electronic system |
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| GB2280293A (en) * | 1993-07-19 | 1995-01-25 | Hewlett Packard Co | Wafer scale architecture for programmable logic |
| US5396126A (en) * | 1993-02-19 | 1995-03-07 | At&T Corp. | FPGA with distributed switch matrix |
| EP0748052A1 (en) * | 1995-06-07 | 1996-12-11 | International Business Machines Corporation | Continuous address structure with folding |
| WO1998055918A1 (en) * | 1997-06-04 | 1998-12-10 | Dynachip Corporation | Fpga with conductors segmented by active repeaters |
| US20010014965A1 (en) * | 1997-03-27 | 2001-08-16 | Takefumi Hiraga | Automatic global routing device for efficiently determining optimum wiring route on integrated circuit and global routing method therefor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5327023A (en) * | 1991-03-28 | 1994-07-05 | Kawasaki Steel Corporation | Programmable logic device |
| US6191611B1 (en) * | 1997-10-16 | 2001-02-20 | Altera Corporation | Driver circuitry for programmable logic devices with hierarchical interconnection resources |
-
2003
- 2003-06-17 CN CNB038153726A patent/CN100559377C/en not_active Expired - Fee Related
- 2003-06-17 EP EP03735912A patent/EP1520298B1/en not_active Expired - Lifetime
- 2003-06-17 US US10/519,767 patent/US7355443B2/en not_active Expired - Fee Related
- 2003-06-17 AU AU2003237005A patent/AU2003237005A1/en not_active Abandoned
- 2003-06-17 AT AT03735912T patent/ATE483251T1/en not_active IP Right Cessation
- 2003-06-17 DE DE60334380T patent/DE60334380D1/en not_active Expired - Lifetime
- 2003-06-17 JP JP2004517107A patent/JP4283220B2/en not_active Expired - Fee Related
- 2003-06-17 WO PCT/IB2003/002743 patent/WO2004004008A1/en not_active Ceased
- 2003-06-26 TW TW092117426A patent/TWI300980B/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5396126A (en) * | 1993-02-19 | 1995-03-07 | At&T Corp. | FPGA with distributed switch matrix |
| GB2280293A (en) * | 1993-07-19 | 1995-01-25 | Hewlett Packard Co | Wafer scale architecture for programmable logic |
| EP0748052A1 (en) * | 1995-06-07 | 1996-12-11 | International Business Machines Corporation | Continuous address structure with folding |
| US20010014965A1 (en) * | 1997-03-27 | 2001-08-16 | Takefumi Hiraga | Automatic global routing device for efficiently determining optimum wiring route on integrated circuit and global routing method therefor |
| WO1998055918A1 (en) * | 1997-06-04 | 1998-12-10 | Dynachip Corporation | Fpga with conductors segmented by active repeaters |
Also Published As
| Publication number | Publication date |
|---|---|
| US20050257947A1 (en) | 2005-11-24 |
| US7355443B2 (en) | 2008-04-08 |
| DE60334380D1 (en) | 2010-11-11 |
| JP4283220B2 (en) | 2009-06-24 |
| CN1666341A (en) | 2005-09-07 |
| EP1520298A1 (en) | 2005-04-06 |
| ATE483251T1 (en) | 2010-10-15 |
| EP1520298B1 (en) | 2010-09-29 |
| JP2005531964A (en) | 2005-10-20 |
| TW200400609A (en) | 2004-01-01 |
| WO2004004008A1 (en) | 2004-01-08 |
| AU2003237005A1 (en) | 2004-01-19 |
| TWI300980B (en) | 2008-09-11 |
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