KR880001171B1 - Addressing device with sequential word order - Google Patents

Abstract

No content.

Description

Addressing device with sequential word order

1 is a diagrammatic representation of a system including a memory system including an apparatus of the present invention.

FIG. 2 shows in detail the lines of the system bus 10 in contact with the memory subsystem of FIG.

3 is a block diagram of the memory subsystem 20-1 of FIG.

4A-4C illustrate in greater detail other portions of the memory subsystem 20-1 shown in FIG.

5 is a timing diagram used to describe the operation of the present invention.

FIG. 6A illustrates an address format applied to the memory subsystem of FIG.

FIG. 6B is a diagram illustrating a configuration of the memory module shown in FIG.

FIG. 6C is a diagram illustrating a configuration of the memory modules shown in FIG.

* Explanation of symbols for main parts of the drawings

10: Multi-wire bus 20-1 ~ 20-n: Memory subsystem

40: central processing unit (CPU) 200-1: controller

204: Timing unit 205: Refresh control unit

206: data control unit 206-8, 206-10: data register

206-16, 206-18: multiplexer circuit 207: address section

208: lead / light control unit 210: memory unit

210-2, 210-4: 256K Wared Memory Module

210-20: Even Memory Unit or Even Stack Unit

210-40: Odd Memory Unit or Odd Stack Unit

210-22 to 210-26, 210-42 to 210-46: address buffer circuit

211: bus control unit 212: memory initialization unit

213: bus driver / receiver circuit section 215: queue control section

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory systems, and more particularly to an addressing device therefor.

It is well known to construct a memory system using multiple memory modules. In prior art systems, memory modules are configured to be paired together to provide double word fetch access capability.

The term "double word fetch access" as used herein refers to the ability to access a pair of words at a time from the memory system during one cycle of operation. This type of system was invented by Jhon L. Curley, Robert B. Johnson, Richard A. Lemay and Chester M.Nibby, Jr., patented November 25, 1980 and then assigned to the assignee. System Providing Multiple Fetch Bus Cycle Operation "is described in US Pat. No. 4,236,203.

The prior art system allows the memory system to be connected to a single word bus that operates asynchronously. In such a system, a request for multiple words is made in a single bus cycle and the required information word is sent to the bus through a series of response cycles. Such a system improves system-wide capabilities, but is able to provide two worded accesses simultaneously through a single bus cycle.

In such a paired memory module system, it is necessary to generate even and odd addresses so that the paired memory modules can be accessed. The system for generating such addresses was invented by Robert B. Johnson and Chester M.Nibby, Jr., and entitled "A Dynamic Memory System Which Includes Apparatus for Performing, patented on January 22, 1980, and then assigned to the assignee. Refersh Operations in Parallel with Normal Memory Operations "is described in US Pat. No. 4,185,323.

In the above system, the lower bit for the address where the memory request is provided specifies the storage location being accessed, while the upper bit specifies that the row of the RAM chip is being selected. To extract the two words of the accessed pair, it is necessary to increment the memory request address by one and then decode the incremented address. This is necessary for the memory addressing device to include a primary address register, which also serves as a counter, and two parallel secondary address registers for storing the initial address and the incremented address received from the primary address register. Such a device allows handling of memory requests that originate on certain word boundaries (ie, allow even or odd word calls). The device doubles the amount of storage in the address register and increases the delay in generating even and odd addresses to access the paired memory module starting as either module.

Other addressing devices used in combination with a pair of independently addressable memory modules are Robert B. Johnson, Chester M. Nibby, Jr. And "Sequential Word Aligned Address Apparatus," which was invented by Dana W. Moore and filed on January 8, 1980, and assigned to the assignee, is described in co-pending patent application 110,521. In order to reduce the delay in generating the addresses, the apparatus utilizes the least significant or lower address bits of the memory request address to specify which row of the RAM chip contains the first word location to be accessed. In response to these address bits, the decoding circuit generates a pair of output signals to simultaneously select a pair of words from a pair of modules. The address circuit includes a pair of address registers and a multi-bit adder circuit operated in three states for storing row and column address portions of a memory request address. Each time the least significant address bit has a value indicating a sub-boundary condition, the adder circuit increments the lower row address bits by one to enable the desired pair of word position accesses.

The incremental operation described above can delay the overall performance of the memory, since the time allocated to each addressing operation must include the time required for the address increment.

The decoding circuit in the above addressing device increases memory performance by eliminating the need to increment the address while not in a sub-boundary condition, which is reduced in situations where sub-boundary conditions frequently occur due to different memory organization.

It is therefore an object of the present invention to provide a memory system that generates addresses for reading a pair of words from a pair of memory modules.

Another object of the present invention is to provide a method and apparatus for minimizing circuitry and delay to provide addresses for reading at least a pair of words from a memory system coupled to multiple word buses.

The above and other objects are attained from the preferred embodiment of the memory subsystem of the present invention comprising at least one pair of memory module units that are coupled to multiple word buses through separate data register circuits in operation and are independently addressable. Each of these memory module units includes multiple rows of random access memory (RAM) chips.

By means of the present invention, the address associated with each memory request received by the memory subsystem is encoded such that the most significant or upper address bits specify which row of the RAM chip contains the first word to be accessed. The next lower order or lower address bits specify the RAM chip addresses of the first word location to be accessed.

The memory subsystem includes a common addressing circuit and a common timing circuit. The address circuit includes a pair of address registers and a multi-bit adder operated in three states to store row and column address portions for the chip address of the memory request address received from the bus. The output terminals of the two registers are commonly connected with address lines applied to other memory module units to multiplex the address. In addition, the lower address lines applied to the register storing the column address partial unit to which even memory addresses are allocated are applied in parallel with the addition circuit. The output of the addition circuit is also applied to the multiplexer circuit which is connected to receive the lower row address bits applied to the register which stores the row address portion. The output of this multiplexer circuit is contacted as the lower address bit source for the memory module unit to which even addresses are assigned.

In response to a memory request, the timing circuit adjusts an address register and a multiplexer circuit to successively apply row and column addresses to address lines of a memory module unit to access multiple sequence warped positions. Generate a signal. That is, the lower row address bits are transmitted to the even memory module through the multiplexer circuit. In parallel with this transfer, the altered or unchanged lower column address bits are passed through the adder circuit and then transferred to the even memory module through the multiplexer circuit, while the address bits of the column address portion of the memory module unit Is applied to the address lines.

In the case of a memory read request, a number of words are simultaneously read through an output multiplexer circuit into a data register circuit connected to word lines of a number of word buses. The multiplexer circuits selectively apply multiple words to a group of word lines during a single bus cycle operation depending on the state of the least significant address bit.

That is, an even or odd word may be applied to each word line as a function of the lowest address bit value. Similarly, the data register circuit and the multiplexer circuit connected to the multiple word buses allow the words received from the bus to be written into the correct memory module unit via the data register circuit during the write operation.

During the transfer of the row address portion, whenever the least significant address bit has a predetermined value indicating the sub-boundary address state, the adder circuitry accesses the lower column address bits that access the desired sequential pair of word positions in the memory module unit. Increment by 1

However, each time a memory request specifies an address representing an actual boundary address condition, the boundary circuit causes the timing circuit to generate only a timing signal for accessing a plurality of first word positions as soon as the address condition is detected.

The above-described apparatus can provide the addresses necessary to simultaneously access multiple sequential word positions in multiple memory module units during a minimally delayed single bus cycle operation.

This is accomplished without adversely affecting system performance. In other words, instead of incrementing the row address portion normally transmitted first to the memory module unit, the addressing device of the present invention operates to increment or change the column address portion while transferring the row address portion to the memory module unit. Thus, the column address portion can be transmitted without any delay since the result of the incremental operation has already been completed.

In a preferred embodiment, the 3-bit adder increments the chip address by 1 for every different word (eg, when the least significant bit has the value "1"). Thus, boundary conditions occur on the basis of word 15 or modulo 16. By increasing the adder size, the boundary conditions can be further extended.

Further features and novel features of the construction and method of operation together with the additional objects and advantages of the present invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted, however, that the accompanying drawings, which are given for purposes of illustration and description, are not to be construed as limiting the invention.

General description of the system of FIG.

1 illustrates a data processing system including the apparatus of the present invention. The system of FIG. 1 includes a multi-wire bus 10 coupled to n memory subsystems 20-1 through 20-n and a central processing unit (CPU) 40. As shown in FIG. Only memory controllers are shown in the system of FIG. 1, but also include other devices such as those described in US Pat. No. 4,000,485, which is commonly patented on December 28, 1976.

The memory subsystem includes memory controllers (ie, 200-1 to 200-n) that address the four memory module units, labeled A through D, respectively.

Central processing unit 40 is a microprogrammed processing unit that may be considered a conventional cell lineage for the purposes of the present invention. A more detailed description of this can be found in the co-pending patent application described above, as well as in the invention by Richard A. Lemay and John L. Curley, filed on January 5, 1978, and assigned to the assignee, "System Providing Multiple." See US Patent Application No. 867,266, entitled "Outstanding Information Requests." See also related patent application entitled "Interface for Controlling Information Transfers between Main Data Processing Systems Units and a Central Subsystem" by George J. Barlow et al.

The central processing unit 40 as well as the respective controller and memory subsystems communicate over the bus 10 in a predetermined manner as described in US Pat. No. 4,000,485. In short, if a unit wishing to communicate requires a bus cycle so that the bus cycle is allowed, the unit will be in the "master" state, allowing any other unit in the system to be addressed as a "slave". In the case of a bus exchange requiring a response (e.g., a memory read operation), the requesting unit as a "master" identifies itself and instructs the "slave" unit that a response is desired. When the slave is ready to respond (for example when it is ready to obtain the desired information), it initiates the transfer of information to the requesting unit, acting as the "master".

Thus, the number of bus cycles varies depending on the type of operation to be performed.

By changing the state of the signals applied to the control line to be described in connection with FIG. 2, one unit can specify the type of cycle or operation to be started or executed by another unit.

A distributed die-breaking network allows bus cycles to solve concurrent requirements for the use of bus 10. The priority is allowed based on the physical location on the bus 10, with the highest priority given to the first unit on the bus. In a typical system, the memory subsystem allows the highest priority and the central processing unit allows the lowest priority so that other units are located based on their performance requirements.

Memory subsystem interface line

Command Description

Address line

The BSAD00-BSAD23 bus address lines constitute a 24-bit wide path used in connection with the bus memory reference line BSMREF to send a 24-bit address to the controller 200 or a 16-bit identifier from the controller 200 to the bus. (For reception by slave unit). When used for addressing memory, the signals applied to line BSAD00-BSAD03 select a particular 512K word module, and the signals applied to line BSAD04-BSAD22 are one of the 512K words in that module. Selects one of the bytes in the selected word (ie, BSAD23 = 1 = right byte; BSAD23 = 0 = left byte). When used for identification, the lines BSAD00-BSAD07 are not used. Lines BSAD08-BSAD23 carry the identifier of the receiving unit sent to the controller 200 during the line memory request.

BSAP00 This bus address parity line is a bidirectional line that supplies an odd parity signal for the address signal applied to lines BSAD00-BSAD07.

Data line

BSDT00-BSDT15, BSDT16-BSDT31 A group of bus data lines constitute a 32-bit or two-word wide bidirectional path for transferring data or identification information between the controller 200 and the bus as a function of the operating cycle performed. During a write cycle operation, these bus data lines carry information to be written into memory at a location specified by an address signal applied to lines BSAD00-BSAD23. During the first half cycle of the lead cycle operation, the data lines (BSDT00-BSDT15) transmit identification information (channel number) to the controller 200. During the second half cycle of the lead cycle, these data lines carry information read from the memory.

BSDP00, BSDP08 BSDP16, BSDP24 These are bus data parity lines, two sets of bidirectional lines that supply odd parity signals encoded as follows.

BSDP00 = odd parity (left byte) for signal applied to line (BSDT00-BSDT07);

BSDP08 = odd parity (right byte) for the signal applied to the line BADT08-BSDT15;

BSDP16 = odd parity for the signal applied to the line (BSDT16-BSDT23)

BSDP24 = odd parity signal for the signal applied to the line (BSDT24-BSDT31).

Control lines

BSMREF This is a bus memory reference line that extends from the bus to the memory controller 200. When set to true, this line informs the controller 200 that the lines BSAD00-BSAD23 contain a complete memory controller address and are performing a write or read operation for a particular location.

When reset to false state, this line informs the controller 200 that the lines BSAD00-BSAD23 contain information sent to a unit other than the controller 200.

The BSWRIT bus wait line extends from the bus to the memory controller 200 which, when set to true, causes the controller 200 to execute a write cycle operation with respect to the true line BSMREF. When reset to a false state, this line signals the controller 200 to execute a read cycle operation with respect to the line BSMREF being true.

BSBYTE This is a bus barit line, which extends from the bus to the controller 200 which, when set to true, causes the controller 200 to perform a barart operation rather than a worded operation.

BSLOCK This is a bus lock line extending from the bus to the controller 200. When set to true, this line sends a request signal to the controller 200 to run the test or to change the state of the memory width flip-flop included in the controller 200.

BSSHBC This is the second half bus cycle line, which is used to signal to the unit that the current information applied to the bus by the controller 200 is the information requested in the read ahead request. In this case, the controller 200 and the information receiving unit are busy communicating to all the units from the start of the initialization cycle until the controller 200 completes the transmission. This line is used to set or reset the memory width flip-flop in relation to the (BSLOCK) line. If the unit requires read or write and line BSLOCK is true, line BSSHBC signals controller 200 to reset the lock flip-flop. When in the false state, it signals the controller 200 to test and set its lock flip-flop.

BSMCLR This is a bus master clear line extending from the bus to the controller 200. When this line is set to true, this causes the controller 200 to clear any bus circuit to zero.

BSDBWD This is a double worded line which is a unidirectional line extending from the controller 200 to the bus 10. This line is used in conjunction with the (BSDBPL) line to indicate how many data words or which formats are provided by the memory controller 200 during a read request. The state of the line BSDBWD during the read response cycle from the memory controller 200 indicates whether one or two words of data are being applied to the bus 10.

When the line (BSDBWD) is in binary 1 state, it indicates that 2 words are being transmitted, and when only one word is transmitted, the line (BSDBWD) is binary O.

BSDBPL This is a double full line, which is a bidirectional line extending between the controller 200 and the bus 10. This line, together with the line (BSDBWB), indicates whether the response was the first (not the last) or last unit of the requested data.

Bus Handshake / Timing Line

BSREQT This is a bus request line, which is a bidirectional line extending between the bus and the controller 200. If set to true, this indicates to the controller 200 that another unit is requesting a bus cycle. When reset to a false state, this informs the controller 200 that there is no bus at all staying on the bus request. This line is made true by the controller 200 to request a second half bus read cycle.

BSDCNN This is a bidirectional line extending between the bus and the controller 200 is a data cycle line. When it is true, this line allows the controller 200 to accept the bus cycle that a unit has requested and transfer the information on the bus to another unit. The controller 200 makes the line true to let it know that it is sending the requested data back to some unit. Prior to this, the controller 200 requires and permits a bus cycle.

BSACKR This is a bus acknowledgment line, which is a bidirectional line extending between the bus and the controller 200. When set to binary 1 by the controller 200, the line signals the controller 200 that it is accepting bus transmissions during the lead first half-bus cycle or the write cycle. During the lead second half bus cycle, this line signals controller 200 the receipt of its transmission when set to binary one by the requesting unit.

BSWAIT This is the bus wait line, which is a bidirectional line extending between the bus and the controller 200. When set to true or binary 1 state by the controller 200. This signals the requesting unit that the controller 200 cannot accept the transmission. The unit then initiates subsequent retries until the controller 200 affirms the transmission. The controller 200 sets the BSWAIT line to true under the following conditions.

1. Busy internal lead or write operation cycles.

2. You are requesting a lead second half bus cycle.

3. Expecting refresh operation.

4. You are running a leaf-session operation.

5. Busy when placed in initialization mode.

When the BSWAIT line is set to true or binary 1 by a unit, this signals the controller 200 that the requesting unit does not accept data and terminates the current bus cycle operation.

BSNAKR This is a bus negative response line, which is a bidirectional line extending between the bus and the controller 200. When this line is set to true or binary 1 state by the controller 200 it signals that it is refusing a specified transfer. The controller 200 sets the line BSNAKR to a true state as follows.

1.The memory lock flip flop is set to binary 1 state,

2. Test and set lock flip-flop as required. (BSLOCK is true, BSSHBC is false).

In all cases, if a memo: lock flip-flop is set, the controller 200 generates a response or results in no response over the BSACKR line or BSWAIT line.

When the SNAKR line is made true by a unit, this signals the controller 200 which unit does not accept data and terminates its cycle operation.

Tie Breaking Control Line

SAUOK-BSIUOK This is a tie breaking network line extending from the bus to the controller 200. These lines signal to the controller 200 whether the units of higher higher priority made a bus request. When all of the signals on these lines are binary ones, this signals the controller 200 that bus cycles were allowed at a time that could bring the BSDCNN line into binary ones. When any of the signals on the line is binary zero, this informs the controller 200 that bus cycles are not allowed, thus inhibiting the line BSDCNN from becoming binary one.

BSMYOK This is a tie breaking network line extending from the controller 200 to the bus. The controller 200 puts this line in a false or binary zero state to inform other units of lower priority bus requests.

General Description of the Memory Subsystem of Figure 1

FIG. 3 illustrates a preferred embodiment of a memory subsystem 200-1 including a controller 200-1 configured using the principles of the present invention. Referring to FIG. It can be seen that the two 256K word memory module units 210-2 and 210-4 of the memory unit 210 are controlled. A circuit in which the high-speed MOS RAM corresponding to the module unit blocks 210-20 and 210-40 of blocks 210-2 and 210-4 is directly integrated. Address buffer circuits corresponding to blocks 210-22 through 210-26 and 210-42 through 210-46. The 256K memory unit is constructed from a 64K word by a 1-bit dynamic MOS RAM chip illustrated in detail in Figure 4c. Specifically, with reference to Figure 4c, each 256 x 22-bit memory module includes 88,65,534 (64K) World x 1-bit chips, each of which has 256 rows x 22 columns of memory cells. There are a number of storage arrays composed of metrics.

The controller 200-1 generates a memory timing signal. Circuits necessary to perform leaf-session operations, control operations, data transfer operations, address distribution and decoding operations, and bus interface operations. These circuits are included as part of the other parts of FIG.

The other units include the timing unit 204, the refresh control unit 205, the data control unit 206, the address unit 207, the read / write control unit 208, the data in unit 209, the bus control circuit unit 211, and the memory. Initialization circuitry 212 and bus driver / receiver circuitry 213.

The bus control section 211 includes circuits for generating signals for generating, adopting and adopting bus cycle requests for single and dual warped operation. As can be seen from FIG. 3, these circuits as well as other negative circuits are connected to the bus via driver / receiver circuit 213 in a conventional design. The bus control circuit section 211 includes a tie breaking network that solves the priority requirements based on the physical location of the unit on the bus. The memory controller 200-1 of FIG. 1 located at the leftmost or bottommost position of the bus 10 is assigned the highest priority, while the central processing unit 40 located at the highest or highest position of the bus. ) Is assigned the lowest priority. For further information on bus operation, see US Pat. No. 4,000,485, issued December 28, 1976.

Timing section 204, shown in detail in FIG. 4A, includes circuitry for generating the required timing signal sequences from memory read and write operations. As shown in FIG. 3, the timing unit 204 includes a refresh control unit 205, a data control unit 206, an address unit 207, a read / write control unit 208, a bus control circuit unit 211, and a bus. Transmit and receive signals from the driver receiver circuit 213.

The address portion 207 shown in detail in FIG. 4B includes circuits for decoding, generating, and distributing signals necessary for the refresh operation, the initialization operation, and the read / write selection. The address unit 207 not only receives a memory reference control signal from the line BSMREF but also receives address signals from the lines BSAD00-BSAD23 and BSAP00. together. The address unit 207 receives control and timing signals from the timing unit 204, the refresh control unit 205, the memory initialization unit 212, and the control unit 215.

The memory initializer 212 includes conventional circuits for initializing or clearing controller circuits to a predetermined state.

The lead / write control unit 208 includes conventional register circuits and control logic circuits. The register circuits receive and store signals corresponding to the states of lines BSWRIT (BSBYIE) (BSDBPL) (BSDBWD) and (BSAD23). In addition, the control logic circuit reads the incoming signal from the register circuits, the controller 200 leads. Signals applied to the timing 204, the address unit 207, and the memory unit 210 to set whether to execute a read accompanied by a write, or a write operation cycle (ie, for a byte instruction). Generate.

The refresh control unit 205 includes circuits for periodically refreshing the contents of the memory. The refresh control unit 205 receives timing and control signals from the timing unit 204 and sends a refresh command to the timing unit 204, the address unit 207, the read / write control unit 208, and the memory initialization unit 212. Supply control signals. For further information on this, see US Pat. No. 1,185,323, which describes circuits for generating a refresh command (REFCOM).

Block 209-4 configured in data portion 209 includes a pair of multiplexers and address registers connected to receive signals from data controller 206. Conventional multiplexer circuits receive data words from two sets of bus lines (BSDT00-15) and (BSDT16-31) and through a set of output lines (MDIE000-015) and (MDIO 000-15) during a write operation cycle. Apply the appropriate word to the correct memory modules. That is, the multiplexer circuits are selectively selected by the signal MOWTES000 generated by the AND gate 209-10 when the initialization signal LNIT 310 from the memory initialization unit 212 is 0 (ie, not in the initialization mode). Is enabled. AND gate 209-10 generates signal MOWTES 000 depending on the function of bus address bit 22 (ie, signal BSAD22) and whether controller 200 performs a write operation (ie, signal BSWRIT). During a write operation, the signal MOWTES000 selects the correct data word to be applied to the correct memory unit (ie, the signal to be applied to the buslines BSDT00-15 or BSDT16-31). This allows for the initiation of a write operation on a given word boundary.

During the read operation, the multiplexer circuits are adjusted to reapply the module identification information received from the bus line BDT00-15 to the address busline BSAD08-23. This is done by loading the signals to be applied to the line BDT00-15 to the even data registers 206-8 of the data control section 206. Accordingly, the address register latches of block 209-4 are matched with the module identification information sent over the bus lines BDT00-15. Since this operation is not relevant to the understanding of the present invention, further description is omitted.

The data control unit 206 is associated with the data registers 206-8 and 206-10 operating in three states, and the control circuits for even and odd memory units 210-20 and ( And multiplexer circuits 206-16 and 206-18 that allow data to be written to or read from them. For example, during a double-lead cycle operation, operands or command signals are read from the memory units 210-20 and 210-40 and the even and odd output registers 206-8 and 206-. Enter 10). During the write operation cycle, signals MDIE000-15 and MDI0000-15 are from the bus to the leftmost part of the pair of registers 206-8, 206-10 via data 209-4. It is rolled out and written to an odd or even unit of the memory unit 210.

The controller 200-1 includes an error detection and correction (EDAC) device, each of which is capable of detecting and correcting a single bit error of the data word and without double correction of the data word without correction. It includes sixteen data bits and six check bits that are used to detect and signal. This EDAC device includes two sets of EDAC encoder / decoder circuits 206-12 and 206-14. These circuits are those described in US Pat. No. 4,072,853, filed February 7, 1978. In addition, the data control unit 206 enables the return of the identification information received from the data line BADT00-15 and stored in the register 209-4 through the address line BSAD08-23.

The queue control unit 215 is also included as part of the control unit 200-1. This queue control section 215 includes circuits for storing address and control information for simultaneously processing a plurality of memory request signals. As can be seen in FIG. 3, the queue controller 215 is a control signal from the timing unit 204, the refresh control unit 205, the address control unit 207, the bus control circuit unit 211, and the memory initialization unit 212. Receive The queue control unit 215 controls signals applied to the timing unit 204, the data control unit 206, the address control unit 207, and the read / write control unit 208. Since the operation of this circuit is not so necessary for the understanding of the present invention, detailed description is omitted.

Now, the relevant parts of the above-mentioned parts will be described in detail with reference to FIGS. 4A to 4C.

Detailed description of filed parts

Only those parts deemed necessary for the understanding of the present invention are described herein. Further information on the remaining parts may be found in related patent applications or in US Pat. No. 4,185,323.

Timing circuit section 204 and address circuit section 206

4 illustrates the timing unit 204 in more detail. This circuit receives input timing pulse signals DLYINN 010, TTAP01010 and TTAP02010 from a normal delay line timing generator circuit (not shown). This circuit is obtained from the configuration of the timing generator circuit shown in US Pat. No. 4,185,323. The timing generator circuit generates a serial timing pulse through a pair of serially connected 200 (ns) delay lines in response to the signal MYACKR010 converted to binary one. Together with the circuitry of these pulse address circuitry 204, the timing for the remaining portions is set during the memory operation cycle.

In addition, the circuits of the timing circuit unit 204 receive the address signals LSAD 22200 and LSAD22210 and the boundary signal MYBNDY 010 from the address circuit unit 207. The memory initialization unit 212 also applies an initialization signal INITMM100 to the timing unit 204. The signal MYBNDY 010 is applied to the NOR gate 204-5 which, when binary 1, causes the signal RASINH010 to be binary 0. The serially connected AND RPDLXM 204-7 logically combines the initialization signal INITMM 100 and the refresh command signal REFCOM 100 generated by the circuit into the refresh control unit 205 to generate a signal RASINH 000. The NAND gate 204-8 combines the signal RASINH 000 and the address signal LSAD 22210 to generate an even row stove prohibition signal ERASIH 000. This signal is applied to the AND gate 204-10 to couple with the timing signal MRASTT 010 derived from the signal DLYINN 010 via the AND gate 204-1. The output signal MRASTE 010 is applied to the even stack unit 210-20 RAS timing input.

The NAND gate 204-14 combines the signals RASINH 010 and LSAD22200 to generate an odd row inhibit signal ORASIH 000. This signal is combined with the timing signal MRASTT 010 at the AND gates 204-17 to generate the row timing signal MRAST 0010. This signal is also applied to the RAS timing coupling of the odd stack units 210-40.

As can be seen in FIG. 4A, the AND gate 204-11 has an even data register 206-8 in the absence of a refresh command (i.e., signal REFCOM 000 = 1) and a timing signal (G) at the middle G input terminal. MDOECT 000) is applied. Similarly, the AND gate 204-15 applies the timing signal MDOOCT 000 to the G input terminal of the middle portion of the odd data register 206-10. The AND gate 204-3 combines the signals MRASTT 010 (REFCOM 100) and TTADO 1010 to generate a timing signal MCASTT 010. This signal MCASTS 010 is applied to the CAS timing inputs of the even and odd stack units 210-20, 210-40 via AND gates 204-18.

Similarly, the AND gates 204-19 generate the timing address signal MCASAD 010. The signal MCASAD 110 is applied to the address circuit of the address circuit section 207 via the AND gate 204-20.

Even and odd data registers 206-8 and 206-10 operate in three states. Specifically, these resistors constitute D type transparent latch circuits such as SN74S373 type manufactured by Texas Instruments. These register circuits are transparent, meaning that while the signal applied to the G input is binary 1, the signal at the Q output terminal follows the signal applied to the D input terminal. That is, when the signal applied to the G input terminal is locked, the signal at the Q output terminal is latched. The output terminals of registers 206-8 and 206-10 are commonly connected with an OR array that enables multiplexing of the data word signal pairs. This multiplexing gives the states of signals (MQ2ELB000) (MQ1ELB000) (MDOTSC000) and (MDRELB000) applied to different output control (OC) input terminals of the registers 206-8 and 206-10 shown in FIG. Is achieved. This operation is independent of the latching action of the register flip-flop that occurs in response to a signal applied to the G input terminal.

A series of gates 204-22 to 204-26 connected in series control the states of the signals MDOTSC100 and MDOTSC010. Gates 204-22 receive timing signals DLYINN010 and DLY020100 at the beginning of the lead or write cycle to enable identification memory to be drawn from the bus. Since this is not necessary for the understanding of the present invention, it can be considered that the signal PULS20210 is in the state of binary zero. During the read operation, the read command signal READCM000 becomes binary zero so that the signal MDOTSC100 becomes binary zero by the AND gates 204-26.

The signal MDOTSC100 enables the middle portions of registers 206-8 and 206-10 when binary 0, and outputs their contents to their output terminals. During the write operation, when the lead command signal READCM000 becomes binary 1, the AND gates 204-26 cause the signal MDOTSC100 to be binary 1. This results in the opposite of the above. That is, the signal MODTSC100 prevents the middle portions of the registers 206-8 and 206-10 from outputting their contents to the output terminal.

The leftmost portions of registers 206-8 and 206-10 are enabled to lower their contents to the output terminal when signal MDRELE000 is binary zero. For the purposes of the present invention, the signal MDRELB000 is assumed to be in binary one state.

Thus, the rightmost parts of the registers are prohibited from applying their contents to the output terminal.

The leftmost two portions of the registers 206-8 and 206-10 are controlled in accordance with the states of the signals MQ1ELB000 and M12ELB000 generated by the queue control unit 215. The signal MDOTSC000 is the leftmost two of either registers 206-8 or 206-10 as a function of the signal Q1TRST010 (Q2TRST000) status from the queue control unit 215 when its logic is binary zero. Enable one of the dogs. When the signal Q1TRST010 is binary 1, the signal Q2TRST000 is binary 0, and the queue control unit 215 causes the signal MQ1ELB000 to be in a binary state. This enables the Q1 portions of registers 206-8 and 206-10 so that the contents are applied to the output terminal. Conversely, when signal Q1TRST010 is binary zero, signal Q2TRST000 is binary one, and queue control section 215 causes signal MQ1ELB000 to be binary zero. This enables the Q2 portion of registers 206-8 (20-10) to apply its contents to the output terminal.

Address circuitry 207

4B illustrates other portions of the address circuit portion 207. As shown, the address circuit section 207 includes an input address section 207-1, an address decoding section 207-2, and an address register section 207-4.

Address section 207-1 and address decoding section 207-2

The input address section 207-1 includes registers 207-12 for storing the lowest bus address bits 22 and the upper chip select address bits 4,5. These three signals are loaded into registers 207-12 when the address strobe signal ADDSTR000 becomes binary zero. This happens when the memory is busy (ie, accepting a bus cycle / memory request).

These three address signals are shown as being received from the bus 10 via the bus driver receiver circuit 213 for convenience of description. That is, these address signals may have queue address registers included as part of the address portion 207 as a source. For further information on such cue circuits, see US patent application Ser. No. 202,821 filed October 31, 1980.

The input address portion 207-1 may also include boundary detection circuits, which are blocks 207-15. These circuits include a NAND gate 207-16 that is connected to the D input terminal of the D flip-flop 207-19 through an AND gate 207-18. NAND gates 207-16 receive memory request address bits 22-19 from bus 10. The gates 207-16 cause the output detected boundary signal DBSA 16000 to be binary zero when the address bits 22-19 are all binary one. In all other cases, the signal DBSA 16000 is binary one. The signal BSDBWD 110 is binary 1 when double word transfer is being performed. The signal DBSA 16000 converts the flip-flop 207-19 to binary 1 by causing the AND gates 207-18 to make the output signal BOUNDY 100 to binary 1 when the logic is binary 1. Let's do it. Accordingly, the signal MYBNDY 110 becomes binary 1 to indicate that there is no boundary condition. When the signal DBSA 16000 is converted to binary zero, this causes the signal BOUNDY 110 to be binary zero, converting the flip-flop 207-19 from binary one to binary zero. The signal MYBNDY 110 is applied to the input of the timing unit 204.

As shown, the upper address bit signal LSAD 05210 and LSAD 04210 are applied to the input terminal of the binary decoder circuit 207-20. The least significant bit address signal LSAD 22210 and the complement signal LSAD 22200 generated by the inverter circuits 207-22 are applied to the timing circuit unit 204 and the data control unit 206.

The binary decoder 207-20 is enabled for operation by the ground of the gate G terminal. Each of the four decoding outputs DECOD0000 to DECOD 3000 is connected to the respective NAND gates 207-24 to 207-30. At this time, it should be noted that the zero decoding signal DECOD 0000 is connected to the input of the NAND gates 207-24 that generate the zero row address strobe signal DRAST 0010. Similarly, the one decoding signal DECOD 1000 is connected to the input of the NAND gates 207-26 which generate the one row address strobe signal DRAST 1010. The next sequential decode signal DECOD 2000 is connected to the NAND gates 207-28 that generate the next sequential row address strobe signal DRAST 2010. Finally, the last decoding signal DECOD 3000 is connected to the NAND gate 270-30 which generates the three row address strobe signal DRAST 3010.

The signal OVRDEC 000 is also received from these gate AND gates 207-32. When signal OVRDEC 000 is binary 0, this causes each of signals DRAST 0010 to DRAST 3010 to be binary 1 when either (REFCOM 100) or (INITMM 100) is in the 0 state.

As shown, even and odd row address strobe signals are applied to the RAM chips of even and odd stack units 210-20 and 210-40.

Address register section 207-4

As shown in FIG. 4, the address register section 207-4 has an address section 207 as input to the row address registers 207-40, column address registers 207-42, and adder circuits 207-54. Receive the bus address signals BSAD 06210 to BSAD 22210 applied through the queue address registers.

The gate input terminals of the registers 207-40 and 207-42 are connected to receive the memory busy signal MEMBUZ 010 from the timing unit 204. The OC input terminals of the row address registers 207-40 are AND gates 207-44, interleaver circuits 207-46, and NAND gates 207 in response to signals ITMM 000 (REFCOM 000) (MCASAD 110). And a timing signal (MRASCT 000) generated by -47). The OC input terminal of the column address registers 207-42 is connected to receive the timing signal MCASCT 000 generated by the NAND gate 207-50 in response to the signal INTEREF 000 (MCASAD 110). Signal INTREF 000 is generated by AND gates 207-44 that receive signals INIMTM 00 and (REFCOM 000).

Each of the address registers 207-40 and 207-42 can be configured with a D-type transparent latch circuit such as the SN74S373 type described above. As can be seen in FIG. 4B, the other address output terminals of each set of registers are commonly connected to the OR array to enable multiplication of these address signals. As already explained, this multiplication is achieved by controlling the state of the signal to which registers 207-40 and 207-42 are applied to the output control (OC) input terminals.

More specifically, the output control (OC) terminals enable so-called tri-state operation controlled by circuits 207-44 through 207-50. When each of the signals MRASCT 000 (MCASCT 000) is in binary 1 state, this prohibits certain address signals from being applied to the associated register Q output terminal. Also, as already mentioned, this operation is independent of the latch flip-flop latching operation.

In addition, in the preferred embodiment of the present invention, the address register section 207-4 is a conventional 3-bit binary full adder circuit 207-54 connected in parallel with the address registers 207-40 and 207-42. It includes. The adder circuits 207-54 are connected to increment the lower address bits 19 to 21 by one. More specifically, the input terminals A1-A4 receive the bus address signals BSAD 21210 (BSAD 20210) BSAD 19210 from the queue address registers of the address unit 207. The binary 0 signal is applied to input terminals A8 and B1-B8. The lowest address signal BSAD 22210 is applied to the adder terminal CO as a carry of the signal as shown. As already mentioned, the bus address signals may have queue address registers of the address portion 207 as their source.

Incremental output signals MADD 00111 to MADD 12111 appearing in adder synthesis terminals S1-S4 are applied to one set of input terminals of the multiplexer circuits 207-56. The second set of input terminal multiplexers 207-56 is connected to receive an address signal BSAD 11210 (BSAD 12210) (BSAD 13210) from the queue address registers of the address section 207. This eliminates register delays. The multiplexer circuits 207-56 are enabled by connecting the enable (EN) terminal to ground. The signal MCASAD 110 of the timing unit 204 applied to the gate GO / G1 terminal controls the source selection of the signals applied to the output terminals of the multiplexers 207-56. That is, when the signal MCASAD 110 is binary 0, the address signals BSAD 11210 (BSAD 12210) and BSAD 13210 are sources of the signals MADD 00211 to MADD 02211. When the signal MCASAD 110 is binary 1, the adder signals MADD 00111 to MADD 02111 are the sources of the signals MADD 00211 to MADD 02211.

The horse stack RAM of FIG. 4C is connected to receive the address signals MADD 00101 to MADD 07010 via the address buffer signals 210-46. The even stack RAM of FIG. 4C is connected to receive the address signals MADD 0010 to MADD 07010 via the address buffer signals 210-26 when the signal MCASAD 110 is binary zero. When the signal MCASAD 110 is binary 1, the incremented output signals MADD 00111 to MADD 02111 are applied to the even stack RAM chip instead of the signals MADD 00010 together with the signals MADD 03010 to MADD 07010. do.

Memory unit 210-10 (210-40) (Fig. 4c)

As already mentioned, the even and odd word stacks 210-20 and 210-40 are shown in greater detail in FIG. 4C. These stacks include four rows of 22, 64K 1-bit RAM chips as shown. Each of these 64K chips contains two 32,768-bit memory arrays. Each array consists of a 128-row by 256-column matrix and is connected to a set of 256 sense amplifiers. It can be seen that other 64K chip configurations can also be used. These chips and associated gating circuits are mounted on a daughter board.

The daughter boards respectively output row and column timing signals from the timing unit 204 and two inverters (not shown) connected to receive the corresponding one of the lead / write command signals from the lead / write control unit 208. Four inputs (e.g. 210-200 to 210-206 and 210-400 to 210-406) connected to receive and receive a column decoded signal from the address portion 207. Only chip terminals suitable for understanding the present invention are shown here. The remaining terminals, not shown, are connected according to a conventional method. For further information on this, see US Pat. No. 912,292, filed March 3, 1978.

Description of operation

The operation of the preferred embodiment of the present invention will now be described with reference to FIGS. 1-6C, in particular with reference to the timing diagram of FIG. Each of the units 210-2 and 210-4 includes four 128K modules shown in FIGS. 1, 4c, and 6c. Each unit 210-2, 210-4 may also include the same number of stack units.

Before describing an example of the operation with reference to FIG. 5, first, FIGS. 6A and 6B are referred to. 6 illustrates the format of memory addresses applied to the memory subsystem as part of a memory read or write request. The upper / highest bit positions are coded to identify the memory module / controller to process the request signals. Address bit 4 is used to select that half of 256K (i.e., top or bottom) of the controller memory is being accessed. In addition, address bits 4 and 5 are coded to specify the row of chips selected for the call. These address bits are processed by the circuits of the memory subsystem 20-1 and are not provided to the RAM chips.

Address bits 6-21 specify addresses of 22-bit position pairs in the RAM chip of the pair of modules being addressed. As will be explained in more detail here, these 16 address bits are multiplied by eight address inputs and address input terminals A0-A7 of the RAM chip of FIG. 4C through buffer circuits 210-26 and 210-46. Is applied. As shown, the least significant address bit 22 specifies whether it is an advance and bit 23 specifies a byte within the specified word.

FIG. 6d illustrates the basic word construction of each of the modules of FIG. 6c. Sequential addresses in hexadecimal form are assigned to different word storage locations as shown. That is, as shown in FIG. 6C, the address 0000 is assigned to the word position in row 0 and column 0. As shown in FIG. The next sequential address 0001 is assigned to the word position in row 0 and column 1. Thus addressing proceeds sequentially along columns rather than along rows of chip arrays. Here, as described, this causes the address increment to proceed alongside the addressing.

FIG. 6C illustrates the memory configuration of the modules A to D shown in FIG. As shown, the first 256K wordwords are provided by modules A and C. Also, the next 256K word is provided by modules B and D. These pairs of modules are selected according to the state function of address bit 4 as already mentioned. 6B and 6C will be referred to explaining that the apparatus of the present invention performs sequential wording addressing in the presence of sub-boundary conditions.

5 shows the relationship between different timing and control signals generated by the circuits of the address portion 207 and the timing portion 204 during a single memory cycle operation. As can be seen in FIG. 5, the various signals shown are referenced to a signal MYACKR 010 which initiates a memory cycle operation. Subsystem 20 receives a memory command that includes an address having the format of FIG. 6A. Accordingly, the signal MYACKR 010 is switched to binary one. In response to the signal MYACKR 010, the circuit of the timing unit 204 causes the memory busy signal MEMBUZ 010 to be binary 1, indicating that the memory subsystem is starting a memory cycle operation (i.e., the memory is busy). ).

In response to the memory busy signal MEMBUZ 010, the bus address signals BSAD to BSAD 21210 are locked to the row address registers 207-40 and the column address registers 207-42. That is, signals BSAD 07210 to BSAD 13210 and signal BSAD 18210 are locked to row address registers 207-40. Signals BSAD 14210 through BSAD 21010, BSAD 19210 through BSAD 21210, and signal BSAD 06210 are routed to column address registers 207-42. In addition, the signal MEMBUZ 101 switches the signal ADDSTR 00 of FIG. 4B to binary zero. Accordingly, the least significant address bits BSAD 22110 and the chip select address signals BSAD 04110 and BSAD 05110 are locked to the registers 207-212.

As can be seen in FIG. 4, the stored address signals LSAD 04210 and LSAD 05210 are decoded by the decoder circuit 207-20. As an example, assume that address bits 4-21 are all zeros. Thus, the decoder circuit 207-20 causes the zero decode signal DECOD 0000 to be binary zero. This signal is controlled by the NAND gates 207-24 so that the signal DRAST 0010 becomes binary 1.

As can be seen in FIG. 4C, the signal DRAST 0010 is applied as one input of the NAND gates 210-206 of the even word stack 210-20. The same signal DRAST 0010 is also applied as an input to the NAND gates 210-406 of the ward stack 210-40. When the timing signal MRASTE 010 (MRAST 0010) is generated, the NAND gates 210-206 and 210-406 cause their outputs to be binary zeros. Subsequently, the row address signals stored from the row address registers 207-40 through the address buffer circuits are applied to both row terminals A0-A7 of the RAM chip embedded in the stacks 210-20 and 210-40. This is brought about.

More specifically, the timing circuits of FIG. 4A in response to the signal MYACKR 010 start a cycle operation while the timing signals DLYINN 010 (TTAD 01010) and (TTAD 02010) are generated. According to these signals, the gages 204-1, 204-3, 204-10, 204-17, 204-19, and 204-20, respectively, represent the signals at the time shown in FIG. MRASTT 010) (MCASTT 010) (MRASTE 010) (MRAST 0010) and (MCASAD 010). As mentioned, the row timing signal MRASTE 010 (MRAST 0010), together with the row decoding signal DRAST 0010, generates even and odd row address strobe signals applied to the RAM terminals on both sides of the row of the RAM chip. At this time, the column address signal MCASTT 010 (MCASAD 010) is binary zero.

As can be seen in FIG. 4B, the output signal MRASCT 000 from the NAND gates 207-47 is zero at this time (ie, when the signal MCASAD 010 is binary 0). This is adjusted so that the row address registers 207-40 can apply all zero bus address signals at their input to their output terminals. From there, the address signals MADD 00010-MADD 07010 are applied to the odd stack address buffer circuits 210-46.

As can be seen in Figure 4b, the upper three row address bits are also applied to the even stack address buffer circuits 210-26. That is, since the column address signals MCASAD 110 are binary zeros, these signals are applied through the multiplexer circuits 207-56. The remaining address signals MADD 03010-MADD 07010 are directly applied to the even stack address buffer circuits 210-26 as shown. Therefore, both rows of the RAM chip latch or store all zero row address signals that are 8 bits applied to the terminals A0-A7.

During the RAS time, the adder circuits 207-54 perform the appropriate incremental operation upon receiving the lower three address bits (i.e., the least significant chip address bits A0-A2) according to the state function of the least significant address bits 22. Since bit 22 is binary zero, the lower three address bits pass through unincremented adder circuits 207-54. Therefore, before the CAS time, the result generated by the adders 207-54 appears at the input of the multiplexer circuit 207-56.

As can be seen in FIG. 4A, the gate 204-20 generates the signal MCASAD 110 at the time shown in FIG. 5 in accordance with the signal MACASAD 010. This signal MCASAD 110 is applied to the NAND gate 207-50 and the multiplexer circuit 207-56. The binary one signal (MCASAD 110) causes the multiplexer circuits 207-56 to select address signals applied to two sets of input terminals.

Specifically, when the signal MCASD 010 is converted to binary one, the signal MCASAD 110 is switched to binary one. Accordingly, the bus address signals BSAD 0602 and (BSAD 14210) to (BSAD 21210) are applied to the output terminals of the registers 207-42. At the same time, the registers 207-40 are forbidden from applying bus address signals to their output terminals. Accordingly, the column address signals MADD 00010 to MADD 07010 are applied to the odd buffer circuits 210-46. The incremented lower address bits are applied to the even buffer circuit 210-26 through the multiplexer circuits 207-56. The remaining column address signals MADD 0310-MADD 07101 are directly applied to the even buffer circuits 210-26.

As can be seen in FIG. 4A, the gates 204-18 produce the signal MCASTS 010 at the time shown in FIG. 5 in accordance with the timing signal MCASTT 010. FIG. This signal MCASTS 010 is applied via NAND gates 210-200, 210-204, 210-400 and 210-406. Accordingly, the column address strobe signal is applied to the CAS terminal of the columns of the RAM chip. Thus, the RAM chip stores all zero zero 8-bit string signals that are applied to terminals A0-A7.

In this state, as the memory address signals are all zeros, the contents will be accessed to the storage positions of the memory modules A and C of FIG. 6C defined by the row 0 and column values storing the word 0 and the word 1. This will be followed by Warward 0 and Warward 1 in the Even Data and Odd Data Registers 206-8 and 206-10, respectively, in response to the signals of the signals of Figure 5 (MDECT 000) and (MDOCT 000). . These even and odd data registers 206-8 and 206-10 are enabled by the signal MDOTSC 100 of binary zero and apply an input data signal to its output terminal.

Then word 0 and word 1 through the data out far multiplexer circuits 206-16 and 206-18 according to the status function of the least significant address bits LSAD22 (MUXD00-15) (MUXD 16-31). Is applied. That is, when the signal LSAD 22210 is binary 0, the contents of the even data registers 206-8 are applied to the line MUXD00-15 by the multiplexer circuit 206-16. The multiplexer circuit 206-18 also applies the odd data register contents to the lines MUXD16-31. The inverse of this occurs when the address bit (LSAD22210) is binary one. In this way, calls to both memory module units occur regardless of the word area. As can be seen in FIG. 5, the memory cycle operation is completed when the circuit of the timing unit 204 switches the memory busy signal MEMBUZ 010 to binary zero.

The RAM chip address bits 6-21 are also the same when the value of the lowest address bit 22 is zero. However, when the value of the lowest address is "1", this generates a sub-light address state. That is, when the memory request address specifies that position 1 is accessed, all zero addresses will be stored in the row and column address registers 207-40 and 207-42 again. If there are no adders 207-54, Words 1 and 0 are accessed. However, it is preferable that words 1 and 2 from modules C and A be accessed and read out to the multiple buses 10. In order to complete the access of the desired word pair, the adder circuits 207-54 are adjusted to increment the column address applied to the RAM chips of the even memory unit 210-20 by one.

Specifically, when the signals RSAD 04110 and BSAD 05110 are binary 0, the decoder circuit 207-20 causes the " 0 " decode output signal DECOD 0000 to be binary zero. Thereafter, the NAND gates 207-24 cause the signal DRAST 0010 to be binary one.

Accordingly, the signal DRAST 0010 is used to convert the row address signals applied to the terminals AO-A7 according to the timing signals MRAST 0010 and MRASTE 010 to the memory units 210-20 and 210- shown in FIG. 4C. 40) are loaded into the row 0 RAM chip. However, it should be noted that during the RAS time, the column address applied to terminals OA-A7 is incremented by one by the adder circuit 207-54 when the value of the least significant address bit 22 is "1". Incremental column addresses are applied to even rows of the RAM chip through the multiplexers 207-56. The RAM chips in all rows of odd memory units 210-40 receive unincremented column address signals.

Thus, Words 1 and 2 of Modules C and A shown in FIG. 6C are accessed in accordance with the state function of least significant address bit 22 to the bus 10 via multiplexer circuits 206-16 and 206-18. It is read. As can be seen in FIG. 6B, the first word located at row 0, column 0 is accessed from module C, while the second word located at row 0, column 1 is accessed from module A. FIG. As can be seen from Figure 6b, the desired word with another column address in module A is accessed by incrementing the odd memory request address received from bus 10. Addressing proceeds in this way until the memory request address specifies word 15. In this regard, the area of the adder circuits 207-54 is exceeded. Since it is not possible to provide the correct column addresses, the boundary circuits shown by blocks 207-15 operate to detect the boundary address state and switch the signal MYBNDY 010 to binary zero. That is, the NAND gates 207-16 switch to binary zeros as the bus address bits 22-19 are all ones. Accordingly, the flip-flop 207-18 cuts to the state of binary zero.

As can be seen from FIG. 4A, the signal MYBNDY 010 causes the signal RASINH 000 to be binary one. Accordingly, the NAND gates 204-8 and 204-14 generate a column address strobe prohibition signal ERASIH 000 (ORASIH 000) based on the state function of the least significant address bit 22. Since bit 22 is binary 1, signal LSAD 222000 is binary 0 and NAND gate 204-10 converts signal ORASIH 00 to binary 1. At the same time, the NAND gate 204-8 switches the signal ERASIH 000 to binary zero. Accordingly, the timing unit 204 generates only timing signals necessary for accessing the odd memory modules 210-40. That is, the AND gates 204-17 generate a timing signal MRAST 0010 that causes the row address to be latched into the row of the RAM chip of the memory module C. This is accompanied by the latching of the opening. Thereafter, the contents of the storage position 15 defined by the row and column addresses are accessed in response to the timing signal MDOCT 000 generated by the AND gate 204-15, and stored in the odd data register 206-10. At this time, word 15 of module C is applied to the line MUXD 00-15, and is not applied to any new data lines MUXD 16-31. It will be appreciated that the state of the signal MYBNDY 010 can also be used to signal the occurrence of economic conditions to the central processing unit 40.

Address sequencing and address decoding proceed in the manner described above until a location corresponding to 256K is reached. From that point onwards, bus address bit 4 is switched to binary one. As can be seen in Figure 6c, the decoder 207-20 thus generates signals DRAST 2010 and DRAST 3010 for accessing the next 256K position. Every 16 wards, the detection of address boundary conditions and the extension of each sub-boundary address condition proceed as already mentioned. The only difference is that the rows of RAM chips in modules B and D are enabled instead of modules A and C using signals DRAST 2010 (DRAST 3010) instead of signals DRAST 0010 (DRAST 1010).

It is understood from the foregoing that the addressing device of the present invention can provide simultaneous access to multiple sequential word positions during a single bus cycle operation. Access is achieved by causing the addressing device to increment each odd-numbered address as a function of the least significant address bit of each request during the interval in which the row address portion of the memory request address is transferred and stored in the same row chip in multiple memory modules. Can be. Accordingly, the data word is delivered to the requesting device in a minimum time. The addressing device of the present invention includes a minimum memory register and operates without any adverse effect on the performance of the memory system. The configuration of the present invention also allows dual word access to be initiated using minimal circuitry in accordance with even or odd word addresses in the case of lead / write operations.

Those skilled in the art will appreciate that various changes can be made to the above-described embodiments. For example, the configuration of the present invention can be utilized in conjunction with the addressing device of the patent application under the term "sequential word of order addressing device" invented by Robert B. Johnson et al. In this case, the address incremental delay is reduced. Thus, the address boundary condition can be adjusted by changing the size of the adder circuits 207-54 and modifying the boundary circuits of blocks 207-15.

Thus, the present invention can be used to access any number of storage locations within the corresponding number of memory module units.

So far, only the preferred embodiment of the present invention has been illustrated and described, but various changes can be made without departing from the spirit of the invention as can be seen in the appended claims.

Claims (43)

In a system comprising a central processing unit, coupled in common with a multi-line bus to transfer information during a bus transfer cycle operation, and operating to issue memory request addresses having multiple bitcoded addresses containing row and column addresses, respectively. A memory subsystem for use, each coupled to the multi-bus 10 separately having a set of input address lines, comprising a plurality of rows of RAM chips, which RAM chips address multiple addresses of memory storage. A plurality of independently addressable memory module units (A through D in FIG. 6C), the array of possible addresses, the addressable arrays being divided into a plurality of rows and columns; First and second couplings to the bus to store the row and column addresses respectively for transferring the respective memory request addresses to the memory module unit, and connected to each of the input address lines of the memory module unit. Multiple bit tri-state registers 207-40 and 207-42; Coupled to a bus to receive the lowest row address bits applied in parallel to the second tri-state register, the lowest column address in response to at least one of the lowest address bits during transfer of the row address to the memory unit. Incremental circuit means (207-54, 207-56) operable to modify bits, said first register, said increment circuit means, and input address lines of a predetermined unit of said memory module unit in parallel The first and second coupled to the bus to receive a least significant row address bit and to concurrently access a plurality of sequential storage locations in the plurality of addressable memory module unit arrays within a minimum amount of time during a single bus cycle operation. Parallel with the row and column addresses applied from the register, respectively And a selection circuit (207-56) operable to successively apply the lowest row address bit and the lowest column address bit generated by the incremental circuit means to a predetermined one of the memory module units. Subsystem. 2. The system of claim 1, wherein the subsystem further comprises row address selection means (206-16) coupled to the bus to generate a row address select signal in response to the most significant bit portion of each address. The selecting means comprises a decoder having a plurality of outputs coupled to other ones of said memory module units and a plurality of selection inputs connected to receive a maximum significant digit bit position, said decoder being controlled by said most significant bit. And providing simultaneous access to said plurality of sequential storage locations as a decoded output signal is generated at a predetermined one of said plurality of outputs to store said row address in a pair of memory module units. 2. The system of claim 1, wherein the subsystem further comprises timing means 204 for generating a timing signal of a predetermined sequence in response to each memory request, wherein the timing means comprises the first and second tri-state registers. And the selection circuit means, and the plurality of memory module units, wherein the first register and the selection circuit means are adapted to apply one of the timing signals of the predetermined sequence to apply the row address to the input address line. Controlled by a first state, wherein the selection circuit means and the second register are controlled by another state of one of the timing signals of the adjustment sequence to apply the row address to the input address line, and the plurality of memories The module unit continues the row and column addresses in a row of RAM chips of the plurality of memory module units. To be stored to the subsystem, characterized in that is controlled by the other signal of said timing signal. 4. The subsystem of claim 3, wherein said subsystem further comprises a plurality of data registers (206-8, 206-10), each of which is a different unit of said memory module units, said timing means, and said bus. And a second pair of gates coupled to the first pair of gates coupled to receive the signal representing the most significant address bit and its complement and the second pair of gates coupled to the first pair of gates. A gate is regulated by one of said timing signals to apply a signal to said plurality of data registers for reading to said bus a plurality of sequentially addressed reads during said single bus cycle operation. Subsystem. 5. The system of claim 4, wherein the subsystem further comprises a plurality of multiplexer circuits 206-10, 206-18, wherein the multiplexer circuit is capable of receiving a signal indicating a least significant address bit and its complement. The plurality of other registers on the bus in accordance with a data register, another worder on the bus, and a coding function of the least significant address bit that is coupled to the bus and initiates a read operation as an odd or even word. A sub-system, characterized in that it is adjusted to be able to apply one of the other word of the word. 4. The apparatus of claim 3, wherein the selection circuit means comprises: a first set of input terminals coupled to the bus to receive the lowest row address bits, a second set of input terminals connected to the incremental circuit means, and And further comprising a multiplexer circuit 207-56 having a set of output terminals connected to the lowest input address line, the multiplexer circuit being connected to said timing means to receive one of the timing signals of said predetermined sequence. And further comprising: adjusting by a state change of one of the timing signals to successively apply the row address and column address bits to the lowest address line of a given module of the modules. Subsystem. 7. The apparatus according to claim 6, wherein said incrementing circuit means includes a defective carry input terminal to receive said one least significant address bit, said incrementing circuit means further incrementing an address bit applied to said selection circuit means by one. And operate in response to a predetermined value of each of the least significant address bits. 7. The method of claim 6, wherein the predetermined value of the least significant address bit indicates a sub-boundary address condition that occurs during addressing of the sequential word storage location, and wherein the increment circuit means addresses the next sequential word location address. And operate in response to said respective predetermined value to increment a least significant column address bit. 9. The subsystem of claim 8, wherein the prescribed value is "1". 9. The apparatus of claim 8, wherein the first and second address registers each comprise a predetermined number of steps, the incremental circuit means being parallel to the bus through n register steps storing the lowest address portion of the column address. And further comprising n input terminals coupled, wherein the increment circuit means responds to each of the n lower order column address bits in response to each of the sub-boundary address condition occurrence signals until generating an output address sum representing an actual boundary address condition. And to increment by one. 11. The method of claim 10, wherein the actual boundary address condition corresponds to a value 2n times the frequency of occurrence of the sub-boundary address condition, where n has a value that extends the boundary address condition so as not to affect the performance of a memory subsystem. Subsystem selected. 12. The subsystem of claim 11, wherein the sub-boundary address condition occurrence frequency is 2 specified by the value " 1 " of the least significant address bit. 13. The memory device of claim 12, wherein n is 3 and the boundary address condition occurs in response to a memory request address having a value that is a multiple of a predetermined value representing the number of sequential word positions that can be accessed in pairs during a single cycle operation. Subsystems. 14. The subsystem of claim 13, wherein the predetermined number has a value that is a multiple of 15 to extend the boundary address condition to allow access to 16 sequential word positions. 11. The apparatus of claim 10, wherein the subsystem further comprises boundary circuit means (207-15) coupled to receive a predetermined address bit of the memory request address, wherein the boundary circuit means comprises: And means for generating an output boundary condition signal indicating said boundary address condition when it has a predetermined value corresponding to the address sum. 16. The circuit of claim 15, wherein the boundary circuit means is coupled to the timing means, the timing means comprising a first pair of gates coupled to receive a signal representing a least significant bit and its complement from the address register, The first pair of gates logically combines the output boundary condition signal with the most significant address bit and the complement signal to generate a pair of the other timing signals, and the first pair of gates are coded with the least significant address bit. The row and column addresses are assigned to a chip row of one of the memory module units that are adjusted by the boundary condition signal to generate one of the timing signal pairs specified by A subsystem characterized by memory. Generates a memory address having a multiple bit coded address, commonly associated with a multi-bus, to transfer information during a bus transfer cycle operation, and containing a multi-bit coded address containing coded row and column addresses to specify a storage location within the memory subsystem to be accessed. 10. A memory subsystem for use in a system comprising a central processing unit operative to provide a plurality of lines, each of which is individually coupled to the multi-wire bus 10, having a set of input address lines, comprising a plurality of rows of RAM chips, The RAM chip includes a plurality of addressable arrays of memory storage, and a pair of independently addressable memory module units (A through D in FIG. 6C) which divide the addressable arrays into a plurality of rows and columns; Addressing means coupled to receive the multiple bit address of each memory request from the bus; The addressing means includes a plurality of bit address registers 206-8 and 206-10 for storing the row and column address bits of each of the memory request addresses for the processing duration of the subsystem, and the respective memory request addresses. Coupled to the bus to respectively store the row and column addresses for transfer to the memory module unit, and each connected first and second multiple worded two-state registers of the input address line of the memory module unit ( 207-40, 207-42, and a plurality of bit address registers to receive the least significant column address bits applied in parallel to the second tri-state register, and during the transfer of the row address to a memory unit pair. Increment the column address bit by one according to a coding function of at least one of the lowest address bits An adder circuit 207-54 operable to turn on, the multi-bit address register for receiving the lowest row address bits, the trailing circuit, and the lowest of the address lines of a predetermined unit of the memory module units; The lowest row address bit and the incremented least significant address bit, during the successive intervals coupled to the address line and simultaneously accessing the plurality of sequential storage locations in the array to the plurality of addressable memory module units within a minimum amount of time during a single bus cycle operation. And a selection circuit (207-56) operable to apply a to a predetermined one of said memory module units. 18. The memory device of claim 17, wherein the subsystem is further configured to generate timing signals of a predetermined sequence in response to a memory request, respectively, the first and second tri-state registers, the selection circuit, and the pair of memory modules. And timing means 204 coupled to the unit, wherein the first register and the selection circuit are configured to apply the row address to the input address line during the first interval during the continuous interval. One of the timing signals, wherein the selection circuit and the second register are adapted to apply the column address to the input address line during the second interval during the consecutive intervals. Controlled by different states of the signal, the plurality of memory module units being the RAM of the plurality of memory module units And is controlled by another one of the timing signals to continuously store the row and column addresses in a row of chips. 19. The system of claim 18, wherein the subsystem further comprises row address selection means (206-16) coupled to the bus to generate row address selection signals in response to the most significant bit portion of each address. The selecting means includes a decoder having a plurality of select inputs connected to receive the maximum significant digit bit portion and a plurality of outputs coupled to other module units of the memory module units, the decoder being controlled by the most significant bit portion. And store the row address in the pair of memory module units to generate a decoded output signal at a predetermined one of the outputs to provide simultaneous access to the plurality of sequential storage locations. 20. The system of claim 19, wherein the subsystem further comprises a module unit of the other of the memory module units, the timing means, and a plurality of data registers 206-8, 206-10 coupled to the bus. Wherein the timing means comprises a first pair of gates coupled to receive the least significant address bit and a signal indicating its complement and a second pair of gates coupled to the first pair of gates; The pair of gates are regulated by a different signal of the others of the timing signals so that signals can be applied to the plurality of data registers so that a plurality of addressed words can be read on the bus during the single bus cycle operation. Subsystem characterized in that the. 21. The multiplexer circuit of claim 20 wherein the subsystem is coupled to the bus, different worded portions of the bus, and a plurality of data registers to receive signals indicating the least significant address bits and their complement. (206-16, 206-18), wherein the multiplexer circuitry comprises the different worded portion of the bus in accordance with a coding function of the least significant address bit to enable read operations from odd or even worders. And to adapt another of the plurality of wards to the ward. 20. The apparatus of claim 19, wherein the selection circuit is connected to a first input terminal coupled to the address register to receive the lowest row address bits, a second input terminal coupled to the adder circuit, and to the lowest address lines. And a control terminal connected to said timing means to receive timing signals of said predetermined sequence, said selection circuit being continuous to said lowest address line of a predetermined module of said modules. And adjust according to a state change of one of the timing signal sequences to apply the row address and the column address bits. 23. The apparatus of claim 22, wherein the adder circuit includes a carry input terminal coupled to receive at least one least significant address bit, and each of the least significant address bits to increment a column address bit applied to the selection circuit by one. And is operated in response to a predetermined value of. 23. The apparatus of claim 22, wherein the predetermined value of the least significant address bit indicates a sub-boundary address condition that occurs during addressing of the sequential word storage location, and wherein the adder circuit is next in response to the respective predetermined value. And increment the least significant column address bit to enable sequential wording addressing. 25. The subsystem of claim 24, wherein the predetermined value is " 1. " 25. The apparatus of claim 24, wherein the first and second address registers each comprise a predetermined number of steps, and wherein the adder circuit has n steps for storing the least significant address portion of the column address. And further including n input terminals connected in parallel to the bus, wherein the adder circuit generates the n lowest column addresses in response to the occurrence of the sub-boundary address condition until an output address sum representing an actual boundary address condition is generated. And operate to increment the bit by one. 27. The system of claim 26, wherein the actual boundary address state corresponds to a value that is 2n times the secondary boundary address condition occurrence frequency, where n is a value that extends the boundary address condition so as not to affect the performance of the memory system. A subsystem selected to have. 28. The subsystem of claim 27, wherein the sub-boundary address condition occurrence frequency is 2 specified by the least significant address bit value " 1. " 29. The memory device of claim 28, wherein n is 3 and the boundary address condition occurs in response to a memory request address having a value that is a multiple of a predetermined value representing the number of sequential word positions that can be accessed in pairs during a single cycle operation. Subsystems. 30. The subsystem of claim 29, wherein the predetermined number is a multiple of 15 and has a value that extends the boundary address condition to allow access to 16 sequential word positions. 27. The system of claim 26, wherein the subsystem further comprises boundary circuit means 207-54 coupled to receive predetermined address bits of the memory request address, wherein the predetermined address bits correspond to the address sum. And means for generating an output boundary condition signal indicative of said boundary address condition when it has a predetermined value. 32. The apparatus of claim 31, wherein the boundary circuit means is coupled to the timing means, the timing means including a first pair of gates coupled to receive a signal representing the least significant address bit and its complement from the address register means, The first pair of gates logically combines the output boundary condition signal with the complement and the least significant address bits to generate a pair of the other timing signals, the first pair of gates being further coupled by the boundary condition signal. Generate one of the timing signal pairs regulated and specified by the coating of the least significant address bits to store the row and column addresses in one chip row of the memory module unit pairs so that the first one of the sequential A subsystem for accessing. Used in a system comprising a central processing unit commonly coupled with a multi-bus to transfer information during bus transfer cycle operations and operable to generate a memory request address having a multiple bitcoded address containing row and column addresses. In the memory subsystem, each of which is individually coupled to the multi-bus 10, has a set of input address lines, includes a plurality of rows of RAM chips for storage of data wares, and one module unit is even. An even number of rows containing an addressed storage location, another module unit containing an odd number of rows containing a memory location with an odd address, and the RAM chip comprises a plurality of addressings divided into a number of rows and columns Independently addressable to include a possible memory storage array Number of memory module units (A to D in FIG. 6 (c)); An address register 207-4 for storing a plurality of least significant address bits of each memory request address; A multiple bit tri-state register 207 coupled to the bus for storing the row and column addresses respectively for transferring the respective memory request addresses to the memory module unit and also commonly connected to the lines of the memory module unit. -40, 207-42); A column coupled to the address register to receive the lowest column address bits applied in parallel to the column tri-state register, the column according to a coding function of at least one of the lowest address bits during transfer of the row address to the memory unit pair An adder circuit 207-54 operable to increment address bits by one; An address register for receiving the lowest row address bits applied in parallel with the row address register, the adder circuit for receiving an incremental result of the column address bits, and a data word with the even address. Selection circuits 207-56 coupled to the lowest address lines of the address lines of the memory module unit; Coupled to predetermined input and selection circuits of the row and column three-state address registers to generate a predetermined sequence of timing signals in response to the respective memory requests, wherein the row three state registers and the selection circuit are selected from the timing signals of the predetermined sequence. The row address is transmitted to the memory unit during the row address interval defined by the first state of the one timing signal by being adjusted by one first state, and the column tri-state register and the selection circuit are arranged in the predetermined sequence. Non-incremented and incremented column addresses are transmitted to the memory unit during a column address interval defined by another state of the one of the timing signals, so that even and odd word in the plurality of addressable memory module unit arrays within a minimum time period. Other concurrent access to locations And a memory means (204). 34. The system of claim 33, wherein the subsystem includes row address selection means (206-16) coupled to the bus to generate a row address selection signal in response to the most significant bit portion of each address. The means includes a decoder circuit having a plurality of select inputs coupled to receive the most significant bit portion and a plurality of outputs coupled to other module units of the memory module unit, the decoder circuit being controlled by the most significant bit portion. And generating a decoded output signal to a predetermined one of the outputs to enable the row address storage in the memory module unit to perform simultaneous access to the plurality of sequential storage locations. 34. The apparatus of claim 33, wherein the selection circuit is connected to a first input terminal coupled to the address register to receive the lowest row address bit, a second input terminal connected to the adder circuit, and to the lowest address line. And a multiplexer circuit having a plurality of output terminals, wherein the multiplexer circuit is adjusted according to a state change of the first signal of the timing signal of the predetermined sequence to continuously output the row address and the column address signal during a row and column address interval. And a control terminal connected to said timing means to apply the data word with an even address to said lowest address line of said module unit. 36. The apparatus of claim 35, wherein the adder circuit includes a carry input terminal coupled to receive the one least significant address bit, and further operates in response to each predetermined value of the least significant address bit to thereby select the portion during the row address interval. And incrementing the column address bits applied to the circuit by one. 36. The apparatus of claim 35, wherein the predetermined value of the least significant address bit indicates a sub-boundary address condition that occurs while addressing the sequential wared memory locations according to another column of the memory module unit. And incrementing the least significant column address bit to address the next sequential warward position in response to a predetermined value. 38. The subsystem of claim 37, wherein the predetermined value is "1". 39. The method of claim 38, wherein the row and column address registers each comprise the same predetermined number of steps, and wherein the adder circuitry is stored on the bus with n steps of the column registers for storing the least significant address portion of the column address. And further including n input terminals coupled in parallel, wherein the adder circuit also sets the n least significant column address bits by 1 in response to the occurrence of the sub-boundary address condition until an output address sum representing an actual boundary address condition occurs. A subsystem operable to increment. 40. The apparatus of claim 39, wherein the actual area address state corresponds to a value 2n times the sub-boundary address condition occurrence frequency, where n is a value that extends the boundary address condition so as not to affect the performance of the memory system. A subsystem selected to have. 41. The subsystem of claim 40, wherein the sub-boundary address condition occurrence frequency is specified by the value " 1 " of the least significant address bit. Generating memory request addresses, including multiple bit addresses, commonly associated with multiple buses to transfer datawords during bus transfer cycle operations, and having a row and column address coded to specify storage locations within the memory subsystem to be accessed. A memory subsystem for use in a system comprising a central processing unit operating in such a manner, each of which has a set of input address lines that are individually coupled to other word portions of the multi-bus bus 10 and store the data word. Includes a plurality of rows of RAM chips for the purpose, the N / 2 module unit includes an even row containing storage locations with even addresses, and the N / 2 module unit includes odd addresses, and the RAM The chip contains a number of addressable memory stores divided into a number of rows and columns. N independently addressable memory module units which can be included with an array; An address register 207-4 for storing a plurality of least significant address bits of each address memory request address; First and second multiple bits having an input and an output, the plurality of inputs being coupled to the bus to store the row and column addresses respectively, the outputs corresponding to the outputs being commonly connected to address lines; Three-state address registers 207-40 and 207-42; At least one of the lowest address bits, each coupled to the address register to receive the lowest column address bits applied in parallel to the second three state address register, and transferring the column address to the N memory module units. N adder circuits operative to increment the column address bits by one in accordance with a coding function of; A corresponding one of the N adder circuits, coupled to the address register to receive the lowest row address bits applied in parallel to the first register, to receive a result of incrementing the column address bits; Coupled in series with the least significant bit address lines of the address input lines of the N / 2 memory module unit containing the data word with the even addresses, wherein the N / 2 selection circuits have a continuous time Operate to apply the lowest address bits of the row and incremented column to the lowest address lines during an interval to simultaneously access multiple sequential even and odd positions in the plurality of addressable memory module arrays within a minimum amount of time. With N selection circuits A memory subsystem, characterized in that. A plurality of memory modules AD each having a plurality of rows of memory chips in which addressable memory locations are arranged in addressable rows and columns, and rows for holding a first address portion of a desired memory location in the memory chip Receives an address register 207-40, a column address register 207-42 for holding a second address portion of the address, and a third address portion which is one of the first address portion and the second address portion. A memory system having an address incrementer 207-54 controlled by a binary control signal applied to selectively increment said third address portion, wherein a) the least significant bit of said address is converted into a binary control signal. And a lead connection to the control terminal of the integrator coupled to the integrator, and b) (i) first the address portion in the register Applying the least significant bit and the third address portion to the integrator at the same time as transferring to the memory chip, and then (ii) transferring the address portion selectively incremented by the integrator in the register to the memory chip. And addressing means (207-56).

Images